From what I've read about AMD's Zen architecture, they've dispensed with the "two single threaded cores per module" architecture and now have SMT allowing two threads in each core according to this, much like "hyper threading" on Intel chips.
If that's the case, and we can expect a 32 core chip to execute 64 threads, then that's an awful lot of threads to keep supplied with data and instructions. In comparison, the biggest Intel Xeon I know about, the E5-2699 v3 has 18 cores, 36 threads, 45MB of last level cache, and 4 memory channels (68GB/sec to RAM). Intel sticks pretty close to that 1.25MB cache per core in their big Xeons. So if you adhered to Intel's apparent rules, a 32 core 64 thread chip would need 80MB of LLC and maybe 6 memory channels. Anandtech estimates 5.7 billion transistors for the big Xeon. Scaling the Intel design from 18 to 32 cores would require over 10 billion transistors! That number leads me to believe that an SMT 32 core 64 thread chip built with 2016 technology would not be practical.
What might be practical is a chip with some "heavy" cores optimized for balls-to-the-wall floating point execution, and other "lighter" cores for lower power integer tasks. This has been done in "octocore" mobile phone chips and called a big LITTLE architecture. The idea is that the OS and various decoding and checksumming tasks can stay resident on the low power light cores, while the heavy cores do things like game physics and photo noise reduction. Because the multiprocessing is not symmetric, the OS kernel needs special rules to assign tasks to cores. Which leads me to wonder if AMD has something like big LITTLE up its sleeve for 32 core Zens.