Looking at the pictures in the slides this looks very similar to a carbon nanotube memory process I worked on at my last job (we might have even been licensing some of the IP from these guys). We were looking for a way to shrink our microcontroller die by moving the EEPROM cells up into the metallization stacks. An additional benefit to this memory was that we would be able to increase the EEPROM memory size 2x (with a second layer of cells) with the addition of just 5 more masking layers and almost no increase in die size.
The process I worked on was nowhere near volume production when I left; but I do know we did have completely functional die with carbon nanotube memory. The one part of the process that was most challenging was dealing with the carbon nanotube spin on process. It took forever to get the right thickness uniformity and once you had it at the correct thickness you were rewarded with a material that had filled in your lithography alignment structures to the point they were almost worthless for the next patterning step. It was pretty cool tech to work on, I am glad it looks like somebody is getting it to work.