The price has nothing to do with the lack of leverage for the fab. In semiconductors, there has been a massive consolidation of vendors as tools become more and more specialized (and thus far more expensive to design).

For example if you want to buy an immersion ArF lithography tool, you have exactly two vendors to choose from. Both 1 2 of these vendors will charge you tens of millions of dollars for a single tool, and both will make no promises about software upgrades, unless you pay for a service contract.

At the next generation if you want to buy an EUV lithography tool, you have exactly one vendor, with a nice long waiting list (of your competitors) to get a tool. So good luck trying to negotiate on the software patches for the PC attached to it. Also the last quote I heard about for one of these tools was actually over 100 Million USD.

I had the same shock seeing something from the RC journal on slashdot. I am glad they are getting the lab up and running as it was all just proposals when I moved away from Rapid City.

I hope going with ARM is successful for them; maybe enough to get them to try to make something to compete with the Tegra in the mobile space eventually.

Robert McNamara had a good quote about this in the Fog of War. If I remember he listed it as a "rule" for a life in politics.

"Never answer the question that is asked of you. Answer the question that you wish had been asked of you."

I always considered the day people stopped using Rubylith to be when we stopped doing layouts "by hand".

I couldn't agree with you more.

I frequently try to talk the more technically inclined high school kids in my family/friends group into seriously thinking about an engineering degree instead of IT or Comp Sci. I got a Computer Engineering degree and initially did some work in the mixed signal design area of emphasis; but finally settled in a career doing the optics for chip fabrication. Having studied engineering fundamentals first, then moving on to how they applied to computing machines has opened up so many more job opportunities than I believe I would have had if I had gone Comp Sci.

I work in the USA for a company that makes chips for Samsung amongst others. Our normal shift is 12 hours on your feet in the fab. (on a compressed schedule, 4 days on 3 days off and then 3 days on and 4 days off, and yes I know China is doing 6/7 days a week as the norm but I also know the quality can/will suffer as we are still cheaper than our outsourced competition for their lack of quality and consistency on a cost per good die metric). Its great money for those of us who work it and many of us sign up for overtime on our days off.

Also more to the point of the article, if you are doing inspections for 12 hours in a row on anything complex, you will suck as an inspector and I would hope Samsung would not accept this as a practice in China (or anywhere for that matter) for the interest of QA for their products but maybe I am asking too much.

I think it might make the world a better place.

I saw a presentation a couple years ago at SPIE that has Intel showing cross sections from a sub 10nm process. They had completely wrapped the gate around the device to get those to work so the transistors were just tubes. In the same presentation, they were also showing that the current / voltage improvements between the 32nm node and the 22nm node were much more like the improvements from the 130nm to the 90nm nodes (65nm to 45nm to 32nm have all leaked too much to get much bang for the buck on the shrinks), so theoretically the next generation 22nm Haswell may see some clock improvements again but we will have to see as there are significant challenges in shrinking the 1st layer of metal interconnect that may sink any improvements in the transistor performance.

Also at this same conference the TSMC CEO was very confident that they could make devices that worked well at 7-8nm; the real question was could you manufacture those in a cost effective way as EUV lithography is too slow and going to triple pattern 193nm immersion is going to to be very expensive.

This story strikes me as more gloomy for Global Foundries. AMD is effectively paying to get out of their stake in the company. Last I knew Global had ST and AMD for major customers only. Now with AMD obviously unhappy with the line yields and slow execution on advanced processing nodes we can only assume that they will at least in the short term be looking to TSMC. If Global is not able to quickly back fill with orders from somewhere else their cost situation is only going to get worse. The only bright point for Global I can see is the 2012 contract not being pay for good die only, something I have never heard of in any other supply agreement in the industry. (I have seen price breaks for yield dips or non-acceptance of yields below a certain point, but nothing like pay for good die only).

Where I think AMD really fell behind was they were not able to afford the kind of R&D on the manufacturing side that Intel does for each new process. AMD basically gave up and is now in the same boat as the rest of the "fabless" companies being 100% dependent on what TSMC or Global Foundries can produce. This is always going to put you at a competitive disadvantage at the very high end. While intel is working on pushing down to 22nm FINFET for the "old" architecture people in the design group are without a doubt working on 16nm and getting sample silicon at this node so they can tune their designs for what the transistors will really look like. When you go fabless you get to figure this out with poor yields while in "manufacturing" at the foundry. Maybe at 130 -65nm this wasn't such a big deal but when you need to make your design work with double or tripple patterned 193nm immersion lithography just figuring out some design rules is no simple task.

Also does anyone know if there is more than 1 vendor in the world that can make fully depleted SOI of the quality needed for 32nm - 28nm on a 300mm wafer? Last I knew this was a major reason behind Intel pushing FINFET instead of the fully depleted SOI.

I agree completely a 32-bit ARM 7 is in a completely different ball park than an AVR Mega. Clearly not targeting the same end applications.

http://www.seamicro.com/node/164 Here is the Seamicro page on the system. Its using the dual core Atoms.

This is a real disadvantage from an IC designer standpoint, I would expect that this is not as much of restriction as they are already contained by in the extreme limits imposed on the design by double (possibly triple in this case) patterning to get down to 22nm.

I did see a TSMC presentation earlier this spring at SPIE showing scaling down to the 1xnm node where they actually had little "pipes" of channel where the gate wrapped all the way around (Think of the gate line in a FINFET going through the "fins", in this the FINs became the gates). In this kind of process, designer would be allowed to modify W again on the transistor by making the pipes larger or having two or three of them as part of your transistor with minimal interconnect.

Props to whoever used the Arrested Development house image on their reviews, its what came up when I clicked it.