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Comment: Sun Microsystems did it in '93 (Score 1) 132

by chorlian (#39644993) Attached to: Multicore Chips As 'Mini-Internets'

XDBus: a high-performance, consistent, packet-switched VLSI bus

This paper appears in:
Compcon Spring '93, Digest of Papers.
Date of Conference: 22-26 Feb 1993
Author(s): Sindhu, P.
Xerox Palo Alto Res. Center, CA
Frailong, J.-M. ; Gastinel, J. ; Cekleov, M. ; Yuan, L. ; Gunning, B. ; Curry, D.
On Page(s): 338 - 344
The XDBus is a low-cost, synchronous, packet-switched VLSI bus designed for use in high-performance multiprocessors. The bus provides an efficient coherency protocol which guarantees processors a consistent view of memory in the presence of caches and IO. Low-voltage swing (GTL) CMOS drivers connected to balanced transmission line traces ensure low power as well as high speed for chip, board, and as backplane applications. The signaling scheme and coherency protocol work together to promote a high level of system integration, while permitting a wide variety of configurations to be realized. These configurations include small single board systems, multiple bus systems, multiboard backplane systems, and multilevel cache systems. The bus is used in several commercial systems including Sun Microsystem's new SPARCcenter 2000 series.

The Internet

The Puzzle of Japanese Web Design 242

Posted by kdawson
from the how-to-pack-five-eggs dept.
I'm Not There (1956) writes "Jeffrey Zeldman brings up the interesting issue of the paradox between Japan's strong cultural preference for simplicity in design, contrasted with the complexity of Japanese websites. The post invites you to study several sites, each more crowded than the last. 'It is odd that in Japan, land of world-leading minimalism in the traditional arts and design, Web users and skilled Web design practitioners believe more is more.'"

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