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Actually while IBM may not do a lot of "pure science". Some of it's breakthroughs in technology have far reaching implications, I'd say something similar with HP. So yes, pure science is not getting the kind of investment it did a while back, yes it could do with more, yes it would help. But I am sure that the kind of work that is being done in pure science nowdays is not the kind that can do with the amount of investment that can be "easily" made.
If there were to be radical shifts - a lot could happen. I guess, but what if scenarios are not particularly useful. Yes we need to do stuff, but the how is much more important. That we need to do stuff has been known for ages.
Also - Europe seems to have more money in pure science - I wonder if some one can get stats about how they have been better off for it. (not a bait - actually curious about the numbers)
- I'm not from any of the above mentioned companies.
Yes, essentially I'd agree with you.
However the thing is this, it's easier to get synthesiseable code in verilog that will correspond to your code directly, if you have experience, that is. However, VHDL seems to be better in my opinion only because it is more structured.
Ok - so the thing is, I've done significant work in both. I kind of liked the fact that VHDL was more structured and readable, however Verilog seems to have more support. Now, apart from this the differences, are mostly in getting synthesiseable results from your code, it's easier to get code match the RTL, like I've already said, if you're working in Verilog, plus synthesisers also have better support for Verilog. However, after getting started on verilog, VHDL is much more attractive in my opinion.
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