Same here mate.
Same here mate.
and my phone can go a whole weekend on standby.
What have your turned on ? My Lenovo A840+ (Android 4.2.2, Octa-core 1.4 GHz Cortex-A7) can withstand almost three weeks (weeks, not days) in standby when with good cell reception but with wifi and data connection off. I only start worrying about charging it (I mean, charge it on the same day, not immediatly) when it reaches about 8% battery.
Shut up, will you ?
Definitely someting went wrong. And this has a high probablility of US military misbehaviour, for reasons so far unknown (MSF claims sending proper GPS coordinates, that's still to be confirmed).
Don't try to make this event softer that it was. People died - people who helped people from dying died. It's not acceptable at all, and some one must be held responsable for it. Don't blame technology, don't blame people. Doesn't matter.
What matters is this is recurrent in US operations (and others).
So shut up at least for a minute. Honour those who have been killed for no actual reason.
> My neighbour saw me climb to an open window and called the cops.
Your dog would have recognised you.
Yes, you're right regarding the overall cost and maintenance. But a Doggie is also your friend, cheers you whenever you get home, misses you whenever you leave.
This is priceless.
> "lies in an area known for its high crime rate. A home security system would afford some peace of mind"
Don't know if any runs Linux (and I sincerly doubt it), but perhaps getting a Doggie would help. For sure, you'll get a few false positives, but overall it's the best security you can get.
And yes, they bark really loud.
You know what's funny ?
There's a lot of control over migration and jobs all over the world (even in Schengen - and look at UK position). They do this supposedly to protect their own citizens, to keep wages at an acceptable level, so on. No one is open to let the system self-regulate. And, as odd as it may seem, in EU its the northern countries that oppose to migrants.
The opposite happens in the finance world: They still believe the system self-regulates, there's absolutely no control over whatever, and we have concrete proof that this system, as it is, is a huge bomb that explodes once in a while. Still, no one wants to change it.
Rich people can move big money, Poor people can not move themselves, because people seek money (it's all about money - unfortunately you need money to live).
> Who are you?
> The new number 2.
> Who is number 1?
> You are number 6
> I am not a number, I am a free man
I am not 1010010111101010100010111101101000101, I am a free man.
US problem is not visa attribution - US problem is same problem as everywhere else: too many people, too few jobs, too much lack of education, too many dreams and too many deceptions.
Labeling people will not only not help, but will make thinks worse.
The Nazi system labeled jews, you still recall for sure.
I read an intresting summary today (I am not sure it's accurate though), but it stated that when The Berlin Wall was torn down in 1989 there were other 16 such walls in the world (not necessarly built same way). Nowadays 65 exist, either already in place or being finished. Last one is between Hungary and Serbia, being finished. This is a border line. Not different from the border you see at any international airport.
Most migrants are not searching for The Ultimate Life, but rather seeking survival.
Labeling them is to treat them as if they were animals - or even worse! I guess I could more easily get a permit for my Dog than one of those migrants can get a Visa for entering the US.
And yes, I am somehow revolted, even with my country, due to how it refuses to receive migrants from North Africa.
nyuzi: "It is running on a single core at 50Mhz on a Cyclone IV FPGA. "
Not too bad, but still far from fast (I consider everything 80MHz on this family to be slow). Perhaps a bit more pipelining would help.
Regarding TFA, there seem to be no frequency numbers, and I see they borrow much from OR1200. Last time I synthesized OR1K, it was painfully slow (like 8MHz on a Spartan-3E device). I think it has evolved in this area though.
And I hate Verilog. I always wonder why they do not use VHDL. But it's a matter of opinion, I guess.
So, now we have to say "machinectl shell systemd-run do make me a sandwich" ?
Looks way more complicated.
Do people have a right to shoot a home invader? Of course.
Of course not. At least not where I live (Europe)
You can shoot someone if it presents a threat to your (or our family) life - and only if that someone is armed (and even then it may not be acceptable). But make sure you are entitled to own and operate a gun.
Shooting someone just because he invaded your home is not acceptable at all. Not even cops can shoot him unless he poses a threat to their life.
You do have fine characterization of building blocks, and even macrocells - those are in datasheet, for most vendors. These timings relate to a single part (with a specific speed grade), locked to process, voltage and temperature (worst case is often used).
But not for routing delays (general-purpose and dedicated [i.e., clock]).
So, indeed, you're absolutely right here.
 For those not aquainted with what "process" means, think about handcrafting - some stuff will have less imperfections, others will more imperfections - IC production is not perfect. This also accounts for worst-case scenarios. Of course, ICs that do not meet minimum quality will be discarded at factory.
Thanks, I will read those links in detail.
I came across Cx quite some months ago, but I recall dismissing it because I found it not production ready.
On a side note, I do happen to work closely with systems requiring DO-254 certification, mostly FPGA and ASIC. Not sure most HLD will easily fit in, but I'm always open to explore and suggest if feasible.
EASA SWCEH-001 memo is probably more detailed on requirements than DO-254. You should read it if you're interested in this area.
A few notes regarding your comment.
This is not actually about an "open toolchain to program an FPGA". It's not actually about programming at all. Let me try to explain here (in a simple way) what IceStorm is, or better, what an open-source can do for the FPGA design flow.
So, you start with a description of your design. Your design usually describes the behavour of your system, which is often done in HDL (Hardware Description Languages), like VHDL and Verilog, or even higher-level ones (SystemC, even Python). But, as with every digital design (imagine classical design with TTL 74/CMOS 40 series), you often need more than "logic" - you may need a PLL, you may need a dedicated multiplier (hey, you don't want to design this by hand with gates and flip flops, do you?), or other complex, often mixed-signal primitives.
FPGAs are basically a set of basic blocks (think again 74/40 series), which can be interconnected almost at will. The blocks actually differ from classic chips: what you'll find in FPGAs [I'll speak about Xilinx but Lattice should be similar] are LUT (Look-Up Tables), which can provide any N-input/Y-output digital function (often 4 to 6 inputs, and one output), and Flip Flops (with enable, set, reset, so on). In addition, FPGA provide "hard IP cores", like PLLs, Multipliers, Serializers, Multiplexers, so on, so on.
Now, to have your design to work on the FPGA, you need to synthesize it - convert the behavioural model into these building blocks (LUTs, so on). This is the first phase - and it depends on the target FPGA because the available IP hard blocks differ from manufacturer to manufacturer, from family to family, and even from small to larger, same family devices. This synthesis process will get you a "netlist" - a list of all used primitives and the interconnections needed between them.
Next step is to place the design - pick up each of those primitives, and choose an instance on the FPGA where it will be assigned. This can be tricky, because routing inside FPGA is not 1-to-all, and timing is more affected by routing than anything else - so you'll want your critical (timing critical) paths to be placed where you can later route signals faster. This is really FPGA dependant, much more than synthesis.
Then you have routing: after placing all primitives, you need to decide how to route all signals (this is very complex, FPGA dependant). After routing is done, you have the whole design for that FPGA done - everyting is placed, routed.
Well, you have not.
The next step is to generate a bitstream, based on the netlist output from Route, that can be sent to the FPGA (usually via JTAG). This is actually where less information is known - where each bit from the bitstream maps inside the FPGA switch fabric or LUT configuration or SRAM cells, others,
Then comes programming: sending the bitstream to FPGA. This is usually simple, and many open tools exist (at least for Xilinx).
Now, do these tools do?
Yosys: Verilog synthesis
Arachne-pr: Place & Route
IceStorm: Last part, which is the hardest - to map the final, routed netlist into the "proprietary" bitstream.
Hope I shed some light on the matter.
And yes, being J1 or any another CPU (like my own ZPUino or XThunderCore) is irrelevant - what's relevant is to prove that IceStorm seems to generate correct bitstreams for this platform.
Don't sweat it -- it's only ones and zeros. -- P. Skelly