missing the point how are the TB chips linked to the chip set? and does each controller have it's own X4 link?
The TB 2.0 chipsets use a x4 PCIe 2.0 link per controller. Guess that means that each pair of two TB ports shares the bandwidth of a controller (6 ports / 3 controllers / 12 PCIe 2.0 lanes total.
Probably not fast enough for external graphics that would outperform the (extremely fast) internal graphics solution but still orders of magnitude more bandwidth than any current external consumer or prosumer storage solution.