As someone who is currently writing up a dissertation dealing with this topic, I can assure you that mil spec is not sufficient. Hardening chips for radiation is completely different from hardening them for other hostile environments, especially when you look at the heavy ion strikes you can get in space.
Radiation effects are generally split into two basic categories, Total Ionizing Dose (TID) effects and Single Event Effects (SEEs). TID results from lots of little ion strikes, which gradually build up charge and/or defects and screws with transistor characteristics. Often the result is that transistors leak a lot more current when off, reducing your margins. Since this takes time to build up, it is highly unlikely that this caused the issues with the probe. Since mil spec chips often have a bit more tolerance for this, mil spec does help, but it does not help enough for long exposures.
SEEs are the result of a single, high energy particle hitting the chip. The area of effect varies greatly depending on the energy of the particle, but the typical results of a strike are than a logic gate or cluster of nearby logic gates end up forced to output the wrong value. Essentially, one or more of your "0"s just became "1"s, and vice versa. If these values happened to be important to the current state of the machine or OS running on it, then congratulations, you just got screwed. The two most common ways to harden a chip against this are temporal redundancy and logic redundancy. Temporally redundant circuits assume that any ion will only upset the logic for a short period of time, and wait for the signal to become stable before storing values. This has been the staple of custom hardened chips for a while now, because it is relatively easy to convert all your flip flops into hardened flip flops, and thus harden the entire circuit.
Logically redundant circuits essentially have 3 copies of the logic that vote to determine the correct value. This was often used in the early days of hardening, since you could just stick 3 chips in there and add some basic voting circuits outside the chips to correct the values. However, as processors got more complex, it became harder and harder to restore their state properly in a reasonable amount of time, so people tended to move to temporal hardening for custom chips, and only used logic hardening for things like FPGAs.
Currently, however, temporal hardening is breaking down, since it doesn't scale well with smaller processes. A heavy ion deposits a fixed amount of charge, but smaller processes have less current flow per transistor, so it takes longer to remove that charge and restore proper operation. Thus, the length of time temporal designs have to wait for the signal to stabilize keeps increasing. This is one of the main reasons why hardened chips lag behind in terms of transistor size and the processes they can use. My graduate research has created a method to do high speed, logically redundant circuits that are highly scalable, meaning that you can automatically create three circuits that vote on the same chip, using commercial synthesis and APR tools to automate the process. I firmly believe that this is going to be the standard once people realize how much faster they can make chips run on new processes.