A derived finite-state machine (FSM) is obvious if an isomorphic finite-state machine existed, even if no one has ever made the derived FSM before.
What do you mean by derived as opposed to isomorphic? The two terms are not exclusive.
So, for example, if some logic lithographed onto a silicon die or downloaded as a netlist into an FPGA causes a computer to paint the screen in red paisley and that's never been done before, it's new... but it might be nonobvious and in fact patent eligible.
It might, or it might not, if, for example, logic for causing the computer to paint the screen in blue paisley has been done before.
The problem is when modes of implementation of the FSM get compartmentalized into logic gates versus sequential imperative instructions, because patentability of FSMs in logic circuits has been established for decades, while patentability of FSMs in sequential imperative instructions has not.
"Has not been established" or "has been established as not patentable"? Also, again, what do you mean by logic gates vs. sequential imperative instructions, because the two are not necessarily exclusive.
And so, you get cases like CLS or Bilski where the judges want to invalidate the patent because it's stupidly obvious, but they have no evidence on the record that clearly establishes what an apparatus or machine is and is not... so they declare it an abstract idea and invalid.
Yes, they do - the patent claims begin with a preamble that states whether they recite a machine or apparatus, or a method. That's presumptively conclusive evidence.
For example, Intel not only patents the lithography process of silicon dies of x86 processors, but the logic circuit therein as well in separate patents. But that logic circuit can be implemented in a sufficiently large FPGA, which has software-like characteristics that strongly resemble loading a different sequential imperative machine-code program into a general-purpose imperative-machine-code processor, but with the key difference being the lack of sequential imperative instructions in the FPGA or lithographed IC (ignoring the sequentialness of pulsed timing waves of concurrent gate-flipping in the progress of computation in the FPGA or lithographed IC.)
"strongly resemble", "ignoring"... Although useful for a doctoral thesis, glossing over steps is usually not acceptable in a legal conclusion.