Your post reads like "How do they know some stars are planets anyways? What makes one sparkly thing in the sky different from all the rest? Unpossible to differentiate."
The background would be that flash might not be scaling well, or might eventually stop scaling, so there are a lot of other types of nifty nonvolatile memory types that would aim to replace it. Magnetoresistive, ferroelectric, phase change, memristors, nanotubes, whatever. That's not to say that those sorts of things can't perhaps escape their niche and make create a whole new class of computing machines based on non-transistor switches, but yeah. First things first.
However, the MacBook Pro's screen was brighter, clearer,
The screen on my Thinkpad W500, after a few years, is TERRIBLE.
I think it's time for a crowdsourced patent challenge web site run by the USPTO where there would be a period of public comment for each patent about to be awarded in order to help underpaid (and I imagine under-resourced) examiners find Prior Art.
A lot fewer patents might be awarded, but ones that are would be genuinely new -- this might also save the world billions of dollars.
and several million dollars later it gets sorted out by the courts
No, not really. Several million dollars later, someone capriciously wins, and then there are equally capricious rounds of appeals.
Can we please have an end to the stupid articles where someone intentionally mis-interprets the abstract or even just the title of a patent and pretends it's some simple thing that's been done for decades to try to drum up anti-patent sentiment? There seems to be one a week or so.
Unlikely. Nonetheless, anti-patent sentiment is a good thing. Far too many people assume there's some sort of fairness or justice to the whole mess, and there isn't.
it's 2012, haven't intel or amd engineers developed algorithms to do the chip design for them?
The thing that I take to heart is that even the most simple digital design task-- factoring a sum-of-products boolean equation, the thing you get from your karnaugh map, into the most optimal logic implementation-- algorithms still can't guarantee that. And that task is just one bit of non-sequential static logic. If computers can't guarantee they're better at that, why assume they're better at synthesizing a pipelined, lookahead, out-of-order watchamacallit?
What I'm talking about here is literally placing down a hundred thousand rectangles in a CAD tool
Well, when you have repetitive structures, 100,000 rectangles isn't really all that difficult.
Can anyone supply a concise explanation of the differences and how it's all done? I'm guessing we're talking about people drawing circuits on acetate or similar and then it's scaled down photo-style to produce a mask for the actual chip?
CPU code is in RTL,verilog,VHDL, whatever-- it's in HDL. Usually these days a synthesis tool or compiler will create chip layout that implements that HDL description in standard cell logic. The standard cells are latches, NAND gates, buffers, SRAM, etc. A software tool will place and route standard cells to implement the HDL in silicon, and then iterate on timing to make sure it's fast enough. Humans don't directly do the placement of standard cells, or route wires between them. In terms of photolithography, the standard cells are the silicon transistors, and the first two levels of metal.
It looks like they're making a mountain out of the fact that the standard cells were placed by hand here, and some of the more regular and important wiring was perhaps done by hand, too. You can often take your human knowledge of where the likely performance chokepoints are and place those carefully, and you can also take your human knowledge of where the wiring congestion will be, and be careful there. You're also perhaps able to wire things a bit more creatively in that you can use wrong-way metal and perhaps less gridding. And then you can still probably tell the algorithms to take care of the rest.
In either case the standard cells themselves are often handcrafted in CAD tools, but sometimes different layout software will make them, too. It's just that with large logic chips, past that point humans are often only in the physical design loop to take care of problems the tools can't solve independently-- like massaging things that come out of synthesis too slow to meet the targeted performance, or mandating certain metal levels will be dedicated to a clock mesh. Sometimes that human intervention is just permitting the tool to suck up more power by using faster standard cells. Other times it would be revisiting the architecture in HDL, but then again throwing it over to a computer to place and route. The humans are not actually moving cells around the chip in a CAD tool.
I don't do the synthesis part of the process myself, so someone can clarify or correct me. The thing I wonder about is why the chipworks guys assume hand placement necessarily takes much longer? Looking at the layout, I'd assume the biggest tradeoff is the size of the core, not time spent on placement. It's routing a gazillion non-regular wires that is hard for humans, not placement. We can still place standard cells in a core without needing years of time, provided it doesn't need to be perfectly area-efficient.
Yes, just like we have CPU-bound software and IO-bound software, we have area-limited and pin-limited chips. Pin-limited chips are where the I/O balls are keeping chips from becoming bigger - you see this as CPUs, SoCs, chipsets and other utility chips (many bus architectures are redesigned to be more conservative on their pin usage - why consume 64 pins when you can use 16).
You sounds like a good advocate for TSVs. That said, defects in memory devices probably don't limit the maximum chip size all that much-- memory devices can contain lots of redundant elements to repair defects. Simple chips/wafer cost considerations--because no one wants to pay much for memory--probably has a lot more to do with it. It's just straight-up cost limiting area, not defect density. And when it comes to the push for 450mm, it's not necessarily higher yield that's expected, but lower cost per chip and higher fab throughput. Yield may actually decrease at first, but processing cost per chip would ideally outweigh that.
No. D1X is just 450mm ready.
Similarly, I think the GlobalFoundries fab in Malta, NY is supposedly "450mm ready" or maybe the annex will be. But regardless, "450mm ready" doesn't mean all that much.
My experience is that things begin to break down with the underperformance quotas after layoffs. It's exactly the issue that at the "thousands of employees" level-- following a layoff, you've removed everyone who was in that lower tier. If you maintain the underperformer quotas after layoffs, you really kill morale. Not only are people pissed that their colleagues got kicked out, they're now looking at a regime that immediately begins sorting out who's next.
My guess would be the ranking system was appropriate whenever Microsoft was hiring at a rapid clip, a bit annoying when hiring slowed, and an absolute kick-in-the-balls to employees once layoffs happened. As with anything MS, a lot has to do with the company "maturing." Well, switching from a system that assumes there are lots of new guys to one that doesn't may be part of that process. As people have said, Microsoft hired compentent people, and good employees were generally the motivated ones. I don't disagree that in any group there will be apathetic people, for whatever reason. Once a company isn't hiring people who somewhat randomly become the apathetic undermotivated people, this system tends to turn otherwise decent employees into those apathetic underperformers. You end up pushing people towards a "why bother" attitude rather than motivating them away from it.