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Comment: Re:This is the box you're looking for (Score 5, Informative) 539

by KnightElite (#32829618) Attached to: Sidestepping A-to-D Convertors For Town Government's Cable TV?
Logged in as non-AC and updated with an actual clickable link:
http://www.vecima.com/products.php?line=1026&item=1083

Disclaimer: I work for Vecima networks, but this system does do exactly what you want, and is already being used in that capacity in many other places, including some hotels.
Microsoft

Microsoft Spends $9 Billion On Research, Focuses On Cloud 133

Posted by ScuttleMonkey
from the time-to-double-down dept.
superapecommando writes to share that Microsoft appears to be going all-out on research in the coming year, with a great focus on the cloud. They're supposedly planning to spend $9.5 billion in R&D; that's $3 billion more than the next-closest tech company. "'Especially in light of the tough difficult macroeconomic times that we're coming out of, we chose to really lean in and double down on our innovation,' [Microsoft COO Kevin] Turner said. Turner contended that Microsoft has more cloud services than any other company, ranging from its consumer email service to hosted enterprise products such as its Dynamics CRM (customer relationship management) system to its Azure cloud operating system. 'We're going to change and reinvent our company around leading in the cloud.'"

Comment: Re:C.J. Cherryh has the most realistic handling (Score 1) 361

by KnightElite (#30480294) Attached to: PhD Candidate Talks About the Physics of Space Battles
Read the Lost Fleet series ( http://en.wikipedia.org/wiki/The_Lost_Fleet ) by Jack Campbell. He's got self-consistently handled space battles, and the same kind of light-hours/light-minutes lag, with fleets of ships essentially making high speed passes at each other, shooting for a miniscule fraction of a second, then turning around and doing it again. Obviously has some fantasy technology like deflector shields and artificial gravity, but still awesome.

Comment: Re:Canadian War Museum - Ottawa Canada (Score 1) 435

by KnightElite (#29059125) Attached to: Science, Technology, Natural History Museums?
Seconding this. I felt much the same. I visited this for the first time about a month ago, and was very impressed. Definitely one of the best museums I have ever been to.

They have a large room with a bunch of military vehicles/artillery as well, spanning from bore loaded cannons to Leopard Tanks and M109 Mobile Guns. Some of these have decent signage (most of the tanks, and vehicles along the outer building wall), while a lot of the stuff in the middle is interesting, but unfortunately not presented with any documentation.

The main galleries, however, are excellent, as described. If you're going soon, there's an exhibit about camouflage that's currently running there, created in conjunction with the Imperial War Museum in London, that was quite interesting. If you're hardcore into museums, as you seem to be, allocate a full day for this one.

Comment: Re:VHDL == history (Score 1) 301

by KnightElite (#28174721) Attached to: VHDL or Verilog For Learning FPGAs?
My workplace is primarily a Verilog shop (FPGA design only, no ASICs), though we're forced to use VHDL on occasion when a piece of IP is written in it, or to interface with Xilinx's EDK toolchain, which is mostly written in VHDL. We haven't switched to using System Verilog, but we do attempt to stick to the Verilog 2001 style coding, instead of the Verilog 95 standard. Verilog 95 makes the same code significantly longer and more annoying to change. Things like generate statements and parameter passing have been in place in Verilog since that standard, and all the toolchains that we've used (Xilinx, Altera, Synplicity) support it, albeit only fully since the latest ISE 11 software release in Xilinx's case. Having only done a minimal amount of VHDL, I can tell you that I can't stand it due to the excessive verbosity that is required to do anything in the language, though one of my wishes is that Verilog removed implicit variable declaration, as occasionally a typo will cause a design not to function correctly, which as mentioned will not happen in VHDL. A compiler option for that one would be nice ;). To answer your question as to which you should teach, I would go with Verilog as I find it's easier to use (which may be bias on my part, having used it far more than VHDL), but make sure that you teach "clean" ways of writing the HDL. I've seen a fair bit of excessively verbose, hard to read Verilog code (a lot of the code Xilinx provides for their parts is like this) which could be a lot cleaner if it was written differently. Another thing that I think would be a useful thing to go over is each step of the FPGA build and what it's actual purpose is. What is the output of the synthesizer? What is the output of the mapper?

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