By definition, a superscalar processor does not need to be instruction re-ordering, speculative execution, or branch prediction. All a superscalar processor needs to do to be called superscalar is to dispatch more than one instruction per clock cycle to redundant functional units on the processor -- the 360's CPU is absolutely superscalar.
Incidentally, you are incorrect other aspects anyway: the Xenon cores DO have branch prediction, just in a significantly diminished capacity compared to what we're used to on the PC (small history tables, simpler logic, etc). The Cell's SPEs have none at all, and rely on "branch hints" instead where the programmer or compiler specifies which path may be likely at any given point. As a result, it also has speculative execution.
But you are correct in that the 360's CPUs -- like the Cell's PPU and SPEs -- is in-order and thus does not re-order instructions. It is up to the compilers to generate optimally ordered instructions, which isn't as big a deal as you may think on a closed-box system with optimized compilers. Back in '03-'04 I worked in IBM's compiler group on this very thing.