We do this as well, with Simulink/Matlab, and LabVIEW. Yeah, it would be great if we all knew VHDL, but then we'd be VHDL programmers, not scientists.
We get things working and tested with (very expensive - trading time for money) hardware in LabVIEW, come up with a Simulink model that matches the LabVIEW, then hand it off to a VHDL guy who generates the FPGA code from that. It would be nice if LabVIEW generated usable VHDL but it doesn't. But it's also nice to have a model to play with, and LabVIEW is better at hardware, Simulink better at modeling.
Even so, it's been a bit of a problem getting the final VHDL FPGA to exactly match the results of the tested hardware-in-the-loop LabVIEW and Simulink simulations. Fencepost errors, quantization mismatches, etc.
If we had just handed the requirements to a VHDL person, maybe we'd have something that worked , but that person would have been the only one who understood it or been able to experiment with it. This way, ten scientists have been able to use, change, model, and eyeball the algorithms, and see the results, without any of them having to learn VHDL.
 maybe not. We tried that experiment, and it almost worked, but the programmer who wrote it moved on to another project before it was debugged, and we were left with code that no one else wanted to start with.