Waaaay towards the end of TFA, it mentions that it's GlobalFoundries who inserted finFETs into the same BEOL (wiring) as their 22nm node and called 22nm+finFET "14nm." It's buried at the end, but it's what supports the whole argument that nodes are "just marketing."

To my knowledge, the node's name was based on the DRAM half pitch. But yeah, it's not that any longer. And in defense of GlobalFoundries, finFET does literally add an extra dimension to the calculation of FET geometries.

I have a convertible Windows 8 laptop, and Firefox needs some work, like the rest of the OS. See, for instance, this bug.

Also, the frigging laptop keeps locking the screen upside down and I have to keep unconverting it and reconverting carefully. Totally awesome.

Maybe go read about it

Your post reads like "How do they know some stars are planets anyways? What makes one sparkly thing in the sky different from all the rest? Unpossible to differentiate."

Yeah, it's basically another nonvolatile memory press release. Sounds close to phase-change memory.

The background would be that flash might not be scaling well, or might eventually stop scaling, so there are a lot of other types of nifty nonvolatile memory types that would aim to replace it. Magnetoresistive, ferroelectric, phase change, memristors, nanotubes, whatever. That's not to say that those sorts of things can't perhaps escape their niche and make create a whole new class of computing machines based on non-transistor switches, but yeah. First things first.

Yes, W500, big huge screen. Terrible screen otherwise.

The screen on my W500 sucks.

The screen on my Thinkpad W500, after a few years, is TERRIBLE.

So where's the iOS version of firefox? Or firefox for the Kindle?

http://peertopatent.org/

No, not really. Several million dollars later, someone capriciously wins, and then there are equally capricious rounds of appeals.

Unlikely. Nonetheless, anti-patent sentiment is a good thing. Far too many people assume there's some sort of fairness or justice to the whole mess, and there isn't.

The thing that I take to heart is that even the most simple digital design task-- factoring a sum-of-products boolean equation, the thing you get from your karnaugh map, into the most optimal logic implementation-- algorithms still can't guarantee that. And that task is just one bit of non-sequential static logic. If computers can't guarantee they're better at that, why assume they're better at synthesizing a pipelined, lookahead, out-of-order watchamacallit?

Well, when you have repetitive structures, 100,000 rectangles isn't really all that difficult.

CPU code is in RTL,verilog,VHDL, whatever-- it's in HDL. Usually these days a synthesis tool or compiler will create chip layout that implements that HDL description in standard cell logic. The standard cells are latches, NAND gates, buffers, SRAM, etc. A software tool will place and route standard cells to implement the HDL in silicon, and then iterate on timing to make sure it's fast enough. Humans don't directly do the placement of standard cells, or route wires between them. In terms of photolithography, the standard cells are the silicon transistors, and the first two levels of metal.

It looks like they're making a mountain out of the fact that the standard cells were placed by hand here, and some of the more regular and important wiring was perhaps done by hand, too. You can often take your human knowledge of where the likely performance chokepoints are and place those carefully, and you can also take your human knowledge of where the wiring congestion will be, and be careful there. You're also perhaps able to wire things a bit more creatively in that you can use wrong-way metal and perhaps less gridding. And then you can still probably tell the algorithms to take care of the rest.

In either case the standard cells themselves are often handcrafted in CAD tools, but sometimes different layout software will make them, too. It's just that with large logic chips, past that point humans are often only in the physical design loop to take care of problems the tools can't solve independently-- like massaging things that come out of synthesis too slow to meet the targeted performance, or mandating certain metal levels will be dedicated to a clock mesh. Sometimes that human intervention is just permitting the tool to suck up more power by using faster standard cells. Other times it would be revisiting the architecture in HDL, but then again throwing it over to a computer to place and route. The humans are not actually moving cells around the chip in a CAD tool.

I don't do the synthesis part of the process myself, so someone can clarify or correct me. The thing I wonder about is why the chipworks guys assume hand placement necessarily takes much longer? Looking at the layout, I'd assume the biggest tradeoff is the size of the core, not time spent on placement. It's routing a gazillion non-regular wires that is hard for humans, not placement. We can still place standard cells in a core without needing years of time, provided it doesn't need to be perfectly area-efficient.

You sounds like a good advocate for TSVs. That said, defects in memory devices probably don't limit the maximum chip size all that much-- memory devices can contain lots of redundant elements to repair defects. Simple chips/wafer cost considerations--because no one wants to pay much for memory--probably has a lot more to do with it. It's just straight-up cost limiting area, not defect density. And when it comes to the push for 450mm, it's not necessarily higher yield that's expected, but lower cost per chip and higher fab throughput. Yield may actually decrease at first, but processing cost per chip would ideally outweigh that.