I understand. An open and free society is pretty easy to destroy (imagine if 1% of the people all decided to kill the other 99 one day).

That said, I think we agree that we are willing to take that risk - that the risks from being free are better than the certainty that comes from a police state.

I guess I'm most saddened that there is no debate.

I assume you mean that as an amusing quip, rather than an actual argument

Keep in mind, this is a justification for stripping us of our rights and keeping us in the dark.

I don't believe there is any external threat worthy of violating the Constitution (violating the Constitution is the greatest threat to our nation). If it's really that scary, they can tell us (we're grown ups).

It's far easier to believe that he saw the power and liked it. That he was lying in order to get elected. If he's not a liar, it's easy for him to show us.

19 nm is 190 angstroms. Transistors have been demonstrated operating at ~20 angstroms feature size.

However, current trends show the market will not generate sufficient revenue to keep pushing on Moore's Law.

Economics will break before physics does.

The "n" in FMAn refers to the number of register arguments:
r1 = fma3(r1 + r2 * r3) vs. r1 = fma4(r2 + r3 * r4)

FMA4 can save you a move or two, depending on where you've got the accumulator now, and where you want it to be.

You, sir, win one internet. Use it wisely.

Uops on P6 were 118 bits: http://www.eecg.toronto.edu/~moshovos/ACA05/read/ppro1.pdf

That would have a slight impact on code density :)

Individually they aren't too bad. Taken all together they create real problems.

64 predicate registers (which is way too many) yields 6 bits per syllable (the Itanium term for instruction). Combine that with 128 int regs (7 bits per) and 3 register operands - you've got 27 bits before specifying any instruction bits.

The impact of the middle one (instruction steering) was also not seen until late in the design cycle. Instruction decode information got mixed in there, so that not every instruction could go to every position. This led to a large number of NOPs inserted into the instruction stream. The final code density for Itanium was significantly lower than RISC (and way under x86).

These factors also work against out-of-order implementations - but there were organizational impediments to that happening anyway...