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Comment Intel should preparel x86 replacement (Score 3, Interesting) 246

This article shows the obvious: Excluding caches, performance per transistor in Intel x86 CPUs is very low. As example, current best performance per clock in the Intel CPUs is the AVX (Core i5/i7 -Sandy and Ivy Bridge-), delivering up to 8 FLOP per cycle with AVX SIMD opcodes (2 SIMD ALUs) while in previous generations was just 4 FLOPS per cycle with SSE2/3/4 (just 1 SIMD ALU). Thats miserable (back in 2000, the Playstation 2 was already capable of FMAC opcodes with 8 FLOPs/clock per SIMD ALU!!!). As example, similar performance with 4 FLOP per cycle with one SIMD ALU, at one fraction of waffer area.

Here is a 50$ ARM general purpose multicore-CPU example for matching 999$ performance of fastests Intel Core i7 (e.g. i7-3770K 3.9GHz (peak), 4 CPU, 8 threads, 2 SIMD ALU/CPU = 8 SIMD ALUs = 64 FLOPs/clock -> 3.9*10^9Hz * 64 FLOP/s = 249.6 GFLOPS:
  • 4 x ARM OooE (e.g. Cortex A9-like) 2.0GHz with 2 SIMD FMAC-capable ALUs/CPU (ALU = 16 FLOPs/clock, i.e. 2 ALUs = 32 FLOPs/clock -> 4 * 2.0*10^9 * 2 * 16 = 256 GFLOPS
  • 4 * 32KB + 4*32KB (256KB) L1 full-speed code and data cache
  • 4 * 256KB (1MB) L2 half-speed cache
  • 2 MB L3 half-speed cache
  • 2 or 3 lane ring bus (cheaper interconnect).

For increasing integer and load/store performance, it could be achieved with pipeline and issue/execution modifications, using more functional units. The limit is to keep the OooE simple enough for avoiding wasting transistor in executing tons of instructions unnecesarily.

Comment Git is not that clever, yet (Score 2) 92

Chrome OS also has an autoupdate feature, however not as powerful, unified & transparent as when simply using git.

"clever" differential updates usually work this way (Chrome browser uses it or used it back in the day):

  • Unpacked blob version 1.
  • Packed blob version 1
  • Unpacked blob version 2.
  • Packed blob version 2.
  • Differential packed blobl version 2, taking version 1 as compression base dictionary (or any other differential scheme).

And Git has can not do that yet, because it uses diff + deflate, having far less scope than, e.g. LZMA with 500MB dictionary (requiring 5GB of memory for compressing it is acceptable if it is done just once per version).

Comment Next step: 40-50$ mobile phones (Score 4, Interesting) 342

Those pads have AllWinner A10/A13 SoC (ARM Cortex A8 @1.2GHz and GPU ARM Mali 400), 512MB of RAM, and 4GB of flash. I see no reason for not having mobile phones with similar technology (the AllWinner A10/A13 is a tiny SoC) for similar price (e.g. Broadcom or Qualcomm could add 3G easily and sell their own cost-killer SoC for smartphones). IMO, is going to change everything, as everyone will be able to have an smartphone.

Comment Re:Huh. (Score 4, Insightful) 470

What trade secret? Published keys were already "published" by Sony, because a defective security implementation. It is like writting a number in the box and forbidding you to tell it to others. Geohot just told others what was the keys for his console, and the fact that these keys were the same for all consoles is just Sony's fault. In my opinion Sony deserves this and much more, because of fuking their customers (I still hold PS3 firmware 3.15, for using Linux, but not being able to play new games, because the *requirement* of firmware update). By the way, I have no intention of buying anything produced by Sony, including their media brands (e.g. Columbia Pictures).

Comment Re:is this the best use of die space & RAM ban (Score 1) 199

At 1920x1080 with 32-bit color, the framebuffer is close to 64MiB. This will typically be refreshed at 60Hz, requiring 3.7GiB/s of memory bandwidth.

You're wrong. 32-bit is 4 bytes, so 1920*1080*4 is 7.9MiB/frame, 474MiB/s at 60FPS. With 20GB/s memories is not such a big problem. Of course, a dedicated bus and memory is better.

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