Disclaimer #1: I work for Xilinx. Disclaimer #2: I used to teach VHDL, back in the late 90's. I too, voted on the IEEE effort for standardization on the synthesizable subset for VHDL, and boy what a waste of time that was. But I digress. Here are some cool reasons why VHDL is better than Verilog. 1. Recursion. You can write recursive hardware components that instantiate smaller versions of themselves. Recursion is cool, but tools hate it. The Xilinx tools complain about it, but will still produce the right hardware. Recursion can be used for Multipliers, adder trees, priority encoders, muxes, and just about anything where divide and conquer actually works. 2. Attributes. VHDL attributes translate straight to EDIF properties, and let you do cool stuff like physical design in an FPGA, EDIF properties in the netlist let you do anything from selecting the power-on state of a flop, to setting the logic function of a lookup table (LUT), or setting the initial value of a RAM. Even better, you can pass LOC (Location) or RLOC (relative location) properties, allowing you to physically place the location of a component in the target device. You can even specify directed routing constraints that lock down the signal path to a specific defined route. Verilog will sort of let you do this, but only in a pragma (code comment). Hence creating relatively placed soft macros controlled by top level generic parameters is possible in VHDL, but not in Verilog. 3. Compile time elaboration of constants. This sounds incredibly obscure, but is actually very powerful. During elaboration, constants are evaluated. Constants can be defined by an arbitrarily complex function call. These functions can perform arbitrary computation, as well as read and write files. A standard trick is to read a hex file from the design directory containing data to load into a RAM or a ROM. I use compile time function calls to do precomputation on stuff where I don't know the generic parameters in advance. An example of this would be a state machine to detect a serial unique word, with the states branches computed at compile time by function calls that calculate the state branches based on a unique word specified in a generic parameter. Or how about CRC's? You see people writing C programs to generate Verilog designs to calculate a CRC, but in VHDL, you can compute the parity matrices directly at compile time given a static CRC as a generic parameter. Once the parity matrix is generated, it's easy to generate the hardware to calculate it. It's a bit trickier to do error correction with a CRC, but also possible. These calculations are hideously difficult in Verilog. 4. Type REAL. VHDL has a floating data type REAL, and even a IEEE library REALMATH to use it with (Sine, Cosine, Tangent, etc). You can do very nice geometry calculations during elaboration with this library. Or, for the EE's, you can do stuff like generate coefficents for a raised root cosine filter in VHDL. Now REAL types can't be synthesized directly, since they have no direct hardware representation.. but REAL can be converted to INTEGERs, and integers can be turned in to real hardware with a precision of up to 32 bits. That's plenty in most cases in an FPGA.
Now having said all that... System Verilog has a LOT going for it, and when the tools catch up to the Language Reference Manual, then it could be an extremely powerful design language. This presentation from DATE 2004 shows why. http://www.systemverilog.org/techpapers/date04_systemverilog.pdf
