Comment Power, MIPS? (Score 1) 160
ARM gets to completely redesign their ISA to be more superscalar friendly.. like what Power and MIPS had for years. They get to do this because they now have huge mind-share from the low-end. It will be interesting if they can really compete at all in the high end. Eventually they will have to compete with things that other vendors have tuned for years, such as cache size and smart cache-prefetching.
MIPS and Power really dropped the ball on the low end and are hurting for it. For MIPS I think the issue is that their ISA is not as powerful as ARM for simple single-issue CPUs. In particular, not auto-increment.
Power does have this (with the pre-add offset to index register), but somehow they never made in the mobile world. Maybe Freescale and AMCC didn't try hard enough.