Comment Why is 3D NAND better? (Score 4, Informative) 127
TFA says:
The move to 32-layer 3D VNAND 3-bit MLC flash brings pricing down to the
which didn't make sense to me. Luckily Anandtech has a non-gibberish explanation:
Rather than increasing density by shrinking cell size, Samsung's V-NAND takes a few steps back in process technology and instead stacks multiple layers of NAND cells on top of one another.
With V-NAND, Samsung abandons the floating gate MOSFET and instead turns to its own Charge Trap Flash (CTF) design. An individual cell looks quite similar, but charge is stored on an insulating layer instead of a conductor. This seemingly small change comes with a bunch of benefits, including higher endurance and a reduction in overall cell size. That's just part of the story though.
V-NAND takes this CTF architecture, and reorganizes it into a non-planar design. The insulator surrounds the channel, and the control gate surrounds it. The 3D/non-planar design increases the physical area that can hold a charge, which in turn improves performance and endurance.
The final piece of the V-NAND puzzle is to stack multiple layers of these 3D CTF NAND cells. Since Samsung is building density vertically, there's not as much pressure to shrink transistor sizes. With relaxed planar space constraints, Samsung turned to an older manufacturing process (30nm class, so somewhere between 30 and 39nm) as the basis of V-NAND.
By going with an older process, Samsung inherently benefits from higher endurance and interference between cells is less of an issue. Combine those benefits with the inherent endurance advantages of CTF and you end up with a very reliable solution. Whereas present day 19/20nm 2-bit-per-cell MLC NAND is good for around 3000 program/erase cycles, Samsung's 30nm-class V-NAND could withstand over 10x that (35K p/e cycles).