One way is to get into the OpenRISC project. You can implement your algorithms in software, and when you have identified the parts that could benefit from being run in hardware, write an IP core that takes care of it, hook it up to the wishbone system bus and write a driver.

License is a big thing. In most cases you want to put your own IPs in the same ASIC, and many companies are afraid of putting GPL code together with their own stuff. The leon and opensparc are available as GPL and as a commercial license that cost quite a bit, while the OpenRISC is LGPL only, which makes it more suitable for commercial interests in this case.

The spartan3an has built-in flash for storing the bitstream, and I think you can put other stuff in there too and access it through SPI. http://www.xilinx.com/support/documentation/user_guides/ug333.pdf might get you started

I'm very interested in that area, but haven't had time to look at it in details. One way to move forward could be to profile drivers and see if there are any heavy number-crunching parts that could benefit from being moved to hardware. In the short run this would require patched drivers to interface the hardware, but in the long run I would like to see completely new interfaces, just as OpenGL defined a HW/SW interface for something that was traditionally done in software

Some of the OpenRISC founders started Beyond semiconductors. They have made ASICs of designs based on the OpenRISC. As it is closed-source, I don't know how far from the original OpenRISC they have deviated. Flextronics have also made OpenRISC ASICs about ten years ago. There are many more, but most are under NDAs.

Yes, there are several ports for different development boards with FPGAs from Actel, Altera or Xilinx.. Here's a list of some boards that are supported by ORPSoC (The OpenRISC Reference System On Chip) http://opencores.org/or1k/FPGA_Development_Boards Most of them contain UART, Ethernet, GPIO, SPI and in some cases HDMI, USB and Flash.

MinSoC support even more boards (http://opencores.org/project,minsoc) but there are less supported peripherals there. Ethernet and UART IIRC

The cheapest ones are about $50 or $60. Think the de0-nano is cheapest

If you want to try out some OpenRISC developing without having to buy a dev board, there is also the OpenRISC architecture simulator or1ksim http://opencores.org/or1k/Or1ksim It supports UART through xterm or telnet, ethernet with TUN/TAP and a framebuffer

You're actually spot on :)

I think it was a tight fit though, so I'm not sure it will fit on smaller spartan 3 FPGAs. Disabling caches and hardware mul/div and stuff like that could help. It's a pretty common board, so if anyone is interested in trying, just drop in to #opencores on freenode and chat with us

The OpenRISC is a lot smaller and simpler than the OpenSPARC and probably a bit slower, as it is a single issue CPU. Haven't seen any benchmarks comparing them though. The advantage is that you can buy a $50 FPGA dev board and start hacking on the OpenRISC. The hardware required for an OpenSPARC dev board is significantly more expensive

It could be done. We have booted Linux for OpenRISC on a dev board with 8MB of RAM. A quick look at the xilinx website shows that their top end Virtex-7 FPGAs have 85Mb of Block RAM which theoretically should be enough if not too much of that is used by the cores. You could also build some extra memory from the Slice FFs But that alternative certainly will be expensive. I don't know if there are cheaper FPGAs that specializes in having a higher memory to logic ratio.

New, is to stretch it a bit as it's about 12 years old by now :) Anyways, it is MIPS-inspired, but not compatible. There has been some discussion about making next version MIPS-compatible, but we chose not too, as we would like to add and remove features that can better fit modern embedded systems. Here's a link to the or1200 spec http://opencores.org/websvn,filedetails?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1200%2Fdoc%2Fopenrisc1200_spec.pdf

I checked my facts, and as you say, Lattice fixed the licensing issues. Also, I wasn't aware of the differences in size between the two. Modularity is one of the things on the todo list for the OpenRISC. Hopefully we can bring it down in size in the future. Sounds like a fun weekend project to do some resource usage analysis between the two. If only there were more weekends :)

Finally a comment that makes sense. The milky mist is a really cool project and deserves all the publicity it's getting. Thinking of buying one to try it out. The problem however is with the LM32. The license is very unclear, and IIRC there are at least three different licenses on the RTL code itself. I'm not even sure that it's really allowed to use it on any other FPGAs than Lattice's. From what I've heard it's also lacking a MMU (could be wrong on this part though) I also agree that there are way too few people working on open source hardware, but at least there is a lot more than there was five years ago. We have opencores for a lot of RTL cores and Dangerous prototypes cover a lot of cool open source hardware stuff on the PCB and MCU side just to mention a few. Open source also makes more sense for hardware in some cases as the verification part often is way more time consuming than the development. We have had much help from students that has chosen to do some formal verification project on the OpenRISC or some of the wishbone cores.

I'm working on the OpenRISC project. That is 100% LGPL and with Linux 3.1 it will be supported in the mainline kernel (along with an ever increasing support for different RTOS's). We are slowly getting there :)

The whole point of RISC CPUs is to be less complex than their CISC counterparts.

Timing errors are always the hardest things to track down. Fortunately we are talking about a fully digital ASIC with one clock domain, except for the memory controller, and some other things I might have ignored. I recently finished a project where we converted a FPGA to an ASIC that had more than 180 clock domains. That, my friend, was hard.

The logic bugs are mostly tracked down in simulation, and on the FPGA prototypes. Remember that the openRISC CPU has been available for some time already, runs Linux 2.6.38 fine and is being used in the industry. The RTL is mostly done except for ASICification of some parts.

The fear of suppliers running out of MCUs is real, I can tell you. Reverse-engineering of chips, and reimplementation in FPGA happens all the time in the industry. It is expensive and time-consuming, so having the source code and constraints around is a big help.

...which is why opencores is asking for donations

1. Push ASIC button

2. Profit

Just kidding :) The CPU itself has been turned into ASICs before, so most of the code is in a good shape. The rest is implementation details and will probably be worked out when the ASIC vendor is chosen.

Verification is always the largest issue when you are building complex systems. One of the benefits of open source however, is that someone might have done it before you. In the case of the OpenRISC CPU, the 80000 (correct me if I'm wrong) regression tests of GCC is being used as one source of verification stimuli. Keep in mind also that the design isn't being created from scratch. The core is about ten years old

This isn't an effort to create the next-generation-273-bit-mega-hyper-threaded-with-DDR-5-and-379-core-subpixel-shader-gpgpu on crack. It's a fairly standard 32 bit RISC SoC, with the main difference that the RTL code is open source, and that the ASIC will be sold at a low cost even in low quantities. Think of how popular the Arduino platform is for example. It has some extra street cred, because the layout is open source. Now this is taken one step further, by using a LGPL:d CPU and peripherals. The quaking-in-their-boots part sounds a bit exaggerated, but still, it is primarily because this hasn't been done before. And if it turns out good, there is an ASIC proven SoC that can be modified and recreated by anyone that doesn't want to pay an ARM or a MIPS license for a 32-bit RISC system. Also, by using a fairly cheap FPGA, a reference board with either the ASIC or the FPGA can be sold at a reasonable cost.