Think of it as evolution in action. You can stay on one planet while some disaster takes it out. We have lots of choices of disaster, don't we? The human race can continue via those "space nutters".

Sure, we should try to avoid the disaster, etc., but planets are not forever.

I think I've watched the loop 50 times.

Hopefully we'll find out eventually.

I think you are missing the application for an Open gate array.

It is not really for you and your company. You don't have any particular interest in the open part, and thus you and your company don't fit the demographic of the sort of user we would want. We don't need your money. I can do the first runs of this using Mosis and its ilk for chump change, and go from there.

It simply doesn't matter if it's 32 nm or 15 nm or 50 nm. What matters is that the user can completely understand the bitstream and produce their own tools for it. We have no shortage of users who want that.

It doesn't matter if it is on the leading edge in terms of cost, speed, power, thermal efficiency, or size. It matters that it's open.

And maybe we can do something that you can't do with any integrated circuit available to you, which is verify from first principles that the manufactured device is without deliberately hidden security back-doors. Because we don't have intellectual property to hide and thus we don't mind producing it in a way that would make it capable of being examined.

So, I am not particularly worried about what foundry I'll use and whether I can compete on the same playing field as Xylinx and Altera. I have my own playing field, with radically different rules from the ones they are using. I have my own customers to satisfy.

One well-known market would be immediately available and very eager to embrace an open FPGA, namely EE education.

Yes. EE education and academic research.

There is also the security problem. How can you determine from first principles that the chip really contains what it says it does? Insoluble with any commercial component. Maybe we could make ours sufficiently visible.

So, my feeling is that we could get a grant for this.

There's a partial list of fabs at Wikipedia. There are more than just those three.

Sure, process optimization per fab is an issue. We would probably need to start on the very conservative side.

A lot of the time, building a custom ASIC rather than using an FPGA just isn't an option. Most of the products I'm concerned with need to be programmable.

David Rowe makes a point about echo cancellers and voice codecs, which he's written in Open Source, working alone. They were supposed to be magic. They were supposed to take big expensive research labs to make. When he actually got down to the work, he found there wasn't really magic there. Codec2 can get clear speech into 1200 Baud, and OSLEC (the echo canceler) is part of every Asterisk system and other digital telephony platforms.

Steve Jobs also told me this when I was leaving Pixar. He didn't believe that the Linux guys could make a decent window system, because it had taken a Billion dollar research lab at Apple. Two years later he unveiled Safari, which was derivative of KDE.

There is no question that we can make a good gate array. The technology is very well known. Can we make one that is on the absolute leading edge of the technology? We don't really have to. Making a good one that was open would be enough. But maybe we can make a great one. That depends upon what makes it great. We have a collaborative advantage as far as the software tools are concerned, the same as with compilers. Can we design a really good logic element and fabric? Probably. Can we prototype a gate-array in a gate-array? Sure! Can we use the various devices that OpenCores has developed? I don't think there would be a problem. So we could have on-chip peripherals, CPUs, etc. Once we're sure of it, can it be well-tuned to a fab? Probably, but even if we are conservative about using the fab's capabilities it would work.

Yes. And looking at the way things have gone previously in JEDEC, we would have to be very aware of manufacturers desire to embed their patents in standards.

An Open gate-array is one of those "if you build it, they will come" sort of things. Chinese fabs would compete with each other to drive the price down. It would become the standard low-end part and gate-array manufacturers would have to compete on high-end only.

So I am really interested in doing it, and so is Chris. We just can't ignore our current business in order to do it.

Yes, we feel your pain. Indeed, it's our pain. Proprietary tools, and you get told how to load the bitstream but it's an opaque blob. We would like to work on this problem next. How far off that is I can't say, if we can establish a profitable land-mobile radio business (we don't expect to make much off of hams alone) it would help to fund such an effort.

Chris and I would like to do an Open gate array as our next project. Sufficient patents have expired, etc.

If you ever write a means of describing digital logic designs in Lua we can compare it. Just describing data structures is not sufficient, you need to describe parallel boolean algebraic operations and macrocells such as multiply. At the moment no such thing exists and it would take a long time to duplicate the work of the MyHDL project.

Not sure you understand. The OO model is useful for representing a 4-input device with a logical output determined by a look-up table, which is the fundamental logical element. At least it's useful to do it elegantly. Lua is a small embedded language, but the purpose of MyHDL in this case is not to execute Python at runtime but to generate VHDL or Verilog describing an inherently parallel implementation of an algorithm.

Chris can explain this much better than I, but we are definitely conscious of the gate-array resource use. Currently we are running within the space of the least expensive SmartFusion II chip, which I think you can get for $18 in quantity. Smartfusion 1 was more of a problem as it didn't have any multiplier macrocells and we had to make those out of gates. SmartFusion II provides 11 multipliers in the lowest end chip, and thus the fixed-point multiply performance of a modern desktop chip for a lot less power.

We are also aware of algorithmic costs. For example we were using Weaver's third method and will probably go to something else, maybe a version of Hartley.