I'd say I'm right about in the position you're talking about. I'm getting close to finishing my degree and a lot of the work I've done has been with FPGA's. My introductory class to the area used verilog (although no procedural, code for flip flops was given to us to instantiate). The next course we used VHDL and have used VHDL extensively since then. Both VHDL and Verilog have there strength and weaknesses but overall, for anything an undergrad will be doing, there are no significant difference in functionality. The only real difference I could see coming into play here is which would be easier to pickup.
Verilog has a syntax similar to C. Operators are the same, variable declarations are similar. This is in stark opposition to VDHL that has a syntax that is distinct from anything other language I've ever seen. Then VHDL really contains 2 languages in itself, concurrent and procedural, which for whatever reason have completely different syntax. I still find myself on occasion referencing the syntax for some parts of procedural. So actually learning the syntax, I give it to Verilog. It is familiar looking (I'm assuming everyone taking said class will at least have some background in C) and easy to catch onto.
The real kicker for me to advise VHDL over Verilog is that VHDL is strongly typed where Verilog isn't. Being a beginning class, you can expect the students to make a lot of mistakes. VHDL will complain at compile time and just crash throwing out a million error messages. Verilog will happily try to run it if at all possible meaning you may not find the bug until you've searched through the simulation results which can take a while. This is something that can get prevented(ie. 4 bit addition being stored to a 3 bit variable or comparing an unsigned value to a negative) by VHDL strongly typed nature. At least for me, and probably most students, it's nicer to get the complaint when I compile it than it is to go search for an error in the output.
Lastly, this I'm not as familiar with, but I understand that Verilog is more heavily used in industry whereas most government contracted stuff is done in VHDL. I don't know if this factors into your decision or not.
So my suggestion, if the students seem competent and can avoid simple mistakes, either language will do but Verilog might be slightly quicker to learn. But if it seems that they will be error prone, VHDL is probably the better choice.
