Also more to the point of the article, if you are doing inspections for 12 hours in a row on anything complex, you will suck as an inspector and I would hope Samsung would not accept this as a practice in China (or anywhere for that matter) for the interest of QA for their products but maybe I am asking too much.
Where I think AMD really fell behind was they were not able to afford the kind of R&D on the manufacturing side that Intel does for each new process. AMD basically gave up and is now in the same boat as the rest of the "fabless" companies being 100% dependent on what TSMC or Global Foundries can produce. This is always going to put you at a competitive disadvantage at the very high end. While intel is working on pushing down to 22nm FINFET for the "old" architecture people in the design group are without a doubt working on 16nm and getting sample silicon at this node so they can tune their designs for what the transistors will really look like. When you go fabless you get to figure this out with poor yields while in "manufacturing" at the foundry. Maybe at 130 -65nm this wasn't such a big deal but when you need to make your design work with double or tripple patterned 193nm immersion lithography just figuring out some design rules is no simple task.
Also does anyone know if there is more than 1 vendor in the world that can make fully depleted SOI of the quality needed for 32nm - 28nm on a 300mm wafer? Last I knew this was a major reason behind Intel pushing FINFET instead of the fully depleted SOI.
This is a real disadvantage from an IC designer standpoint, I would expect that this is not as much of restriction as they are already contained by in the extreme limits imposed on the design by double (possibly triple in this case) patterning to get down to 22nm.
I did see a TSMC presentation earlier this spring at SPIE showing scaling down to the 1xnm node where they actually had little "pipes" of channel where the gate wrapped all the way around (Think of the gate line in a FINFET going through the "fins", in this the FINs became the gates). In this kind of process, designer would be allowed to modify W again on the transistor by making the pipes larger or having two or three of them as part of your transistor with minimal interconnect.
Props to whoever used the Arrested Development house image on their reviews, its what came up when I clicked it.
If you really care about what music you listen too while you eat your pizza, why wouldn't you just take it back to your place and eat it there?
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