1) The syntax is incredibly similar to C. Which is why it is always described as "C like" to people who have very little experience in HDL.
The operators are the same as C operators, the comment style is the same and there are semicolons. That is the full extent of the similarity with C. The are no braces (well, there are, but they don't mean what they do in C), macros are different, constants are different, assignment can be different, functions aren't functions, switch statements are case statements, etc, etc... saying that Verilog is "C like" is only going to confuse people who know C. Verilog has more in common with VHDL that with C really (begin and end statements, two difference types of variables, two different ways of doing assignment, both languages have constructs with no C equivalent) and yet people only say Verilog is "C like".
VHDL is better if you absolutely must have full control of the resulting performance on the FPGA.
Ok, I'll bite - what does VHDL give you control over that Verilog doesn't?