Yes necessarily. This isn't some theoretical discussion we're having. This is an actual fab process with actual numbers you can look up right now:
And yet here you are, quoting theoretical numbers. Funny how that works, isn't it? Those densities can only be achieved on highly repetitive structures (aka memory). In reality you cannot achieve that density on actual designs due to yield, thermal and timing concerns. They have little to no meaning for actual general purpose logic, so unless if you're planning to make memory chips you're kind of out of luck.
TSMC has the 3nm node in production. Intel hope to start production at the end 2023. TSMC plans to have its second iteration N3E in production by then. At this stage it looks like TSMC may even get N3E out the door before Intel finishes its Intel 4 node and scales that to full production. It's a node that is beaten in *all* metrics by TSMC's N3 node.
Yes Intel is behind. Intel's CEO even acknowledge they are behind and announced a strategy change to catch up which they hope to do before 2025.
And again, you are blindly staring at process nodes and PR numbers without understanding how to actually compare them.
Let's be quite clear about this, the name and number is meaningless and TSMC could have just as well slapped yoctometer or lightyear behind it. You cannot directly compare transistor density between technologies from different fabs because it ain't a good metric for the practical logic complexity achievable, nor does it indicate actual device performance. The size you're actually interested in is how much surface area you need to implement common digital circuit elements (e.g. common gates, SRAM cells, etc.), and the number of transistors required to implement such an element can vary wildly between technologies, please check the PDKs if you want to get a better idea of these numbers. And that doesn't even consider electric and thermal performance, you can cram all the transistors you want into a certain space, if the leakage current or switching losses are too high, you're going to have a bad time. This is why plenty of devices are manufactured in older technologies as well, the actual performance gain achieved by going to a newer process node can be surprisingly small versus the additional costs made.
And in terms of the CEO acknowledging they're behind, there are two major factors at play there. TSMC has been playing a dirty PR game for the last decade now with process naming and publishing complete bullshit figures, and half of what Intel's been stating publicly is to reduce investor pressure to spin off their fab activities. As to the reason for said pressure, for certain groups of investors it'd be a windfall if Intel would spin off their fab activities. So please learn to take public statements about technology readiness from both TSMC and Intel with a serious grain of salt, there's a lot more to it than most folks seem to realize. And the real gap is more in manufacturing capacity than actual technological performance, but that's not really surprising given the amount of support TSMC is receiving from the Taiwanese government. For added fun, realise that Samsung is breathing down the neck of both, and Samsung is in a class of its own when it comes to throwing money at things to make problems disappear. And that doesn't even consider the fact that UMC, ST and GF aren't quite as far out of the game as you might believe, they are surprisingly competitive in terms of electrical performance for smaller chips and simpler devices. Basically, considering the statements without the context is quite careless.
However, I am also fairly certain that all of this was semi useless and that you're going to quote more garbage from the TSMC fan club/wikichip.
This restaurant was advertising breakfast any time. So I ordered french toast in the renaissance. - Steven Wright, comedian