The new memory element overcomes the longstanding operating trade-off by securing improved speed while reducing power consumption by a whooping 90%. The improved structure is based on perpendicular magnetization and takes element miniaturization to below 30nm. Introduction of this newly designed "normally-off" memory circuit with no passes for current to leak into cuts leak current to zero in both operation and standby without any specific power supply management.
Toshiba expects to bring the new memory element to STT-MRAM cache memory for mobile processors integrated into smartphones and tablets, and will promote accelerated R&D toward that end.
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