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Intel Experimenting With Nanotubes 85

illeism writes "C|Net is reporting on Intel's experimentation with nanotubes in processors. From the article: 'The chip giant has managed to create prototype interconnects — microscopic metallic wires inside of chips that link transistors ... Carbon nanotubes ... conduct electricity far better than metals. In fact, nanotubes exhibit what's called ballistic conductivity, which means that electrons are not scattered or impeded by obstacles.'"
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Intel Experimenting With Nanotubes

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  • Quantum Dots (Score:5, Interesting)

    by googlebear ( 625615 ) <ian@ianroessle . o rg> on Saturday November 11, 2006 @01:40AM (#16802940) Homepage
    Hey this is all really interesting stuff ...I think getting Intel behind some of the manufacturing technicalities is a major boon to the industry. Nanotubes, if intel's research confirms this, should prove to be useful in many different applications from mass power distribution to an elevator to the heavens.. who knows .. stay tunes.. also as an interesting side note.. VLSI will hit a rock bottom soon... I did a presentation in my Nanotechnology class last Spring on Quantum Dot Cellular Automata . This uses the electromagnetic repulsion of electons to propegate signals across molecules that are arranged in such a way to form logic gates.. http://www.nd.edu/~qcahome/ [nd.edu] -Ian ian at ianroessle.org
  • 3D Microprocessors (Score:5, Interesting)

    by AKAImBatman ( 238306 ) * <akaimbatman@gmaYEATSil.com minus poet> on Saturday November 11, 2006 @01:44AM (#16802954) Homepage Journal
    This sounds like it could be of particular use in 3D microprocessor technology. With the number of cores per die ramping up at incredible rates, we're starting to bump into latency issues again. I know that several memory manufacturers (who experinece similar die-space problems) have already switched to layered components to help relieve the issue and keep their dies smaller. But if we can weave nanotubes, we could do a lot more than just stack transistors three or four levels deep. Assuming that a inexpensive manufacturing process were developed, the chip could actually be fashioned in the shape of a cube. The result would make the chip orders of magnitude more dense than the CPUs of today!

    Besides, it would look like a Borg cube under a microscope. How cool is that?!? :P
  • by noigmn ( 929935 ) on Saturday November 11, 2006 @03:23AM (#16803348)

    I'm not sure what is used in processors currently, but having the links as nanotubes would help the heat transfer within the material also. Nanotubes have a thermal conductivity of around 2000-3000 W/m/K at normal CPU operating temperatures. This is a huge increase when you compare it to the 149 W/m/K for silicon and 318 W/m/K for gold at room temperature.

    So the increase in thermal conductivity by just having a proportion of the CPU made from nanotubes could possibly be enough to make up for the shape change. I wouldn't have thought much power would be saved by using nanotubes over any other conductor though. I'd be guessing most of the power loss is in the silicon gates, but I might be wrong.

    http://www.pa.msu.edu/cmp/csc/ntproperties/thermal transport.html [msu.edu] Carbon Nanotube Thermal Conductivity

    http://en.wikipedia.org/wiki/Silicon [wikipedia.org] Silicon Thermal Conductivity

    http://en.wikipedia.org/wiki/Gold [wikipedia.org] Gold Thermal Conductivity

  • by rogtioko ( 1024857 ) on Saturday November 11, 2006 @03:29AM (#16803372)
    Another problem with stacked processors, besides heat, is that to really take advantage of the proximity the interface would have to be changed to one that integrates individual units of each processor more directly. This is far from conventional in terms of normal multicore-chip manufacture and would suffer from non-mainstream extra costs. Still, it should be designed and manufactured: the costs would go down when demand follows.
            I've read that, like 3d microprocessors, memory dies have often been stacked one on top of another (in slower DDR, DDR2 and NAND flash memory). The stacking allows good performance capacity upgrades with limited space; it's more cost effective! If Stacked memory dies sandwich a memory controller, the closer and faster operation would solve a big problem of distance latencies found in the cooperation of single memory dies embedded far apart on a flat circuit board with a memory controller. I could see a mainstream purely stacked memory chip. And if the nanotube interconnect idea works, it could be well implemented in both smaller individual dies and stacked ones.

  • Re:Power is Heat (Score:4, Interesting)

    by CODiNE ( 27417 ) on Saturday November 11, 2006 @04:14AM (#16803496) Homepage
    Actually I remember an article here a while back about nanotubes being used to desalinize water. Apparently the perfectly smooth tubes aid the flow of water and defy the usual "size of pipe is proportional to water pressure" equations. What you could actually do in a 3D chip is leave extra nanotubes built in that simply flow in straight lines through the gaps in the chip where no conductive tubes are located, then pumping fluids through it wouldn't cause problems at all.

    The excellent heat-transfer of nanotubes, plus the efficient water flow through them would make cooling them much better than current chips.

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