AMD Shows Off 1.1 GHz Athlon

chamega writes "AMD demonstrated a 1.1 GHz processor Monday without any special cooling techniques. The processor is said to use "high-performance on-die Level 2 (L2) cache," whatever that means. " Perhaps, unlike Intel, they'll actually be able to /ship/ their high-end chips when they say they will.

...Darn! And I just bought a 600!

Of course, I only paid $240 for my Athlon 600 processor, so I don't feel too deprived.

To the people wondering just how a system with only a 200 MHz bus (and PC100 RAM, at that) can be useful at 1.1 GHz:

First of all, if you're dropping the kind of change on one of these that is appropriate, you'll have more than a puny 64MB of RAM. It's liklier that you'll have at least 128 MB or probably 256 MB+. So you won't have a huge problem with disk thrashing. Just make sure if you were to use one of these beasts that the rest of the system is up to the task. That means a fast ATA or Ultra SCSI disk, a fast 3D card (don't be using no Rage Pro!), and the best memory that the system spec works with. I use all PC-133 nowadays.

On the other side of this is the processor itself. On-die cache (Celerons, CuMine PIII processors) is much faster than the variety that is mounted on the PCB (older PII and III and current Athlons). It can run at full processor clock instead of, say, 1/2 clock or 2/5 clock. Because of this speed advantage, less of it goes a long way. Older PII and PIII designs used 512k of on-board cache, which is replaced by 256k of on-die in the CuMines (128k in the Celery). With a big, fast L2 cache a lot of your instructions are fetched from cache and executed much faster - and of course a big L1 cache helps, too. Also, SDRAM does a better job of feeding data in bursts than older EDO and FP RAM did. But RAM technology is becoming the bottleneck lately. Rambus and DDR SDRAM is supposed to help, but DDR isn't really there yet, and Rambus has been a fiasco to date and the yields are allegedly horrible.

Ultimately, on-die cache allows the cache to run at either full CPU speed or a high divisor of it. PCB cache is more constrained. But faster processors will always make a difference no matter what - it's just that after you outrun the rest of the system it's a matter of diminishing returns. An Athlon 1000 is not necessarily exactly twice as fast as an Athlon 500 - but it's still wicked fast!

- -Josh Turiel

Smokin!

And this is made on .18 fab lines which leaves .13 and .07 yet to come. This processor is going to have so much more in it that Intel isn't going to be able to play the matching gigahertz game much longer. You do have to admire a company that not so long ago had been totally written off and now has processors in most of the Intel strongholds. What's next? PPC overtaking Intel marketshare?

Kryotech

I cannot wait to see what Kryotech is going to do with this bad boy.

If their past patterns hold true, we should see anything from 1.5Ghz to 2Ghz.

Of course, lights will go off all down your street when you fire it up, and you'll be able to go get pizza and Jolt while you're waiting for it come up when you turn it on...

Where is the G spot

Just curious, but are we talking Ghz as in 1024 Mhz or Ghz, as in 1000 Mhz.. :)

"On-Chip L2 cache" whatever that is

L1 cache is the memory closest to the actual computing functions. It runs at CPU speed, but because larger => slower it can't be very big; usually measured in Kbytes. It caches the most-used memory addresses.

L2 cache is larger and slower than L1. Until recently, L2 was implemented by separate RAM devices attached to the CPU. The original Pentium (socket 7) L2 cache was on the processor's front-side bus, between it and the system controller. This became a serious speed limiter and newer processors added a back-side bus strictly for cache (one reason that the CPU modules appeared.) Back-side bus cache runs around 400 MHz plus three or so bus cycles added latency. At 800 MHz this starts to get ugly.

Moving the L2 cache on-chip may not let it run much faster (typically CPU/2 or CPU/2.5) but it cuts the pipeline latency, and latency reduction is what cache is all about. Also, being on-chip makes it much less expensive to use wide busses so the L2 could, for instance, transfer an entire cache line to the L1 in a single cycle.

L1+L2 cache is so good at removing nonrandom accesses from the memory stream that appears on the front-side bus that what actually makes it to the DRAM is almost completely random-access. That's why packet-based memory (e.g., RAMBUS) do so poorly compared to their sustained bandwidth: the bandwidth is never sustained, it's just the first cycle that counts.

For the same reason it's not likely (but you never know) that there's any advantage to adding an off-chip L3 cache. The hit rate would be too low to be worth the trouble of checking for a hit.

Re:... and if that pizza gets cold ...

Heck, you can boil the hot water for your coffee on top of the CPU - then use the CDROM tray as a cup holder!

When will AMD get respect?

With Athlon, AMD has carried the competition to Intel's doorstep. This is the idea. This is what the marketplace is supposed to do. We are supposed to be the beneficiaries.

So I wonder when mainstream PC makers will quit considering AMD to be the cheapo alternative and realize that, at least for the present, they are the performance leaders.