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A Look Into The Cell Architecture
Posted by
timothy
on Sat Jan 22, 2005 10:40 PM
from the between-the-lines dept.
from the between-the-lines dept.
ball-lightning writes "This article attempts to decipher the patent filed by the STI group (IBM, Sony, and Toshiba) on their upcoming Cell technology (most notably going to be used in the PS3). If it's as good as this article claims, the Cell chip could eventually take over the PC market."
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Dupe! (Score:4, Insightful)
Timothy do you actually read Slashdot?
Dupe!-Was it as good for you? (Score:5, Insightful)
Here's a better question. If he will not, why should we?
Parent
Re:Dupe! (Score:5, Insightful)
Wouldn't that be like eating from the toilet?
Parent
Re:Dupe! (Score:3, Insightful)
he's buying the sony propaganda on full throttle, probably wasn't around couple of years when they did the EXACT same thing with ps2 - overhyping it to the max.
it's not some revolution chip that will give you a desktop with 4x the power for cheapo cheap..
A Look Into The Dupe Architecture (Score:2, Funny)
x86 (Score:4, Insightful)
Re:x86 (Score:2, Insightful)
Re:x86 (Score:2)
Re:x86 (Score:5, Interesting)
Parent
Cell IS POWER (Score:4, Interesting)
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Re:x86 (Score:4, Interesting)
I've seen this naive opinion just too often to let another utterance of it escape unchallenged.
64-bit does indeed offer more address space, which is an advantage to those needing more now/soon. But it has more important advantages; with a large, empty address space you can encode permissions, types and other info in pointers. You can pack or aggregate instructions/data. You can more easily/directly share an address space with everyone getting a large portion, or support novel/faster memory layouts by dividing the space into areas with different access permissions in the context of reasonable memory access strides. 32-bit constraints on such techniques make them less generally useful or excessively constrained, but in 64-bit (and above) they could become much more effective. Think of the ways people are proposing to use ipv6 addresses [though there are a few more orders of magnitude difference there] versus the ways people currently use ipv4---an increase in address space can be used for more than just more addresses.
It may require some imagination to exploit it well, but it could have a much larger impact than you (and many others) think.
Parent
You shouldn't do most of this. (Score:3, Interesting)
Re:x86 (Score:3, Funny)
Hell, if Intel's processors get any warmer, I'm going to get the gas cut off and let the computer warm the house.
We need to advance to 64, or 128 bit technology to be able to keep up with other technologies. Cell seems like a logical next step after reading this post a few
Re:x86 (Score:5, Interesting)
That's ridiculous. x86 is dead. The overheating and power consumption confirms it.
CISC hardware is horrible in mobile devices because of battery life and power consumption. Your camera, iPod, cell phone, and PDA do not use x86 hardware.
All next generation consoles will use CISC hardware. Hence, economies of scale to get the price down.
x86 is dead and mobile devices wrote the eulogy.
Parent
Re:x86 (Score:3, Funny)
Until my mobile devices can play Wing Commander, you're full of shit.
Its a dupe (Score:3, Insightful)
Maybe slashcode should have a link repository, if someone adds a new story with a link, they get a warning another story pointing to the same link was posted 18 hours ago...
We've even seen triple-dupes.
Re:Its a dupe (Score:2)
Re:Its a dupe (Score:3, Funny)
Re:Its a dupe (Score:2)
Re:Its a dupe (Score:3, Interesting)
Looks like we need to throw all computers out (Score:2, Insightful)
Re:Looks like we need to throw all computers out (Score:5, Interesting)
He seemed astonished by the 1024 bit wide data paths. The Power family is design with cache fill lines of 128 bytes. So, for instance the G5 L2 cache already does fetches 128 bytes into cache for each main memory read.
Similarly all the talk about doing with cache and VM is bullshit. Instead of having each vector unit interfere with a shared cache as is done today, they've simply added smaller per ALU caches to the design, and complemented it with a device that is a souped up cache controller/MMU unit (the DMAC). The dmac apparently will be able to address both memory, and other hardware by having a virtual address layer, to enable reference to remote cell units as well as local physical hardware. The 64 MB of high speed rambus memory, may be all that is required for a PS3, but in a workstation implementation that memory is L3 cache.
Altivec currently has 32 vector registers. Each ALU as 128. It it highly likely that the core opcode architecture will remain similar. The most likely addition will be to add a few flow control instructions to the existing mix.
Altivec is already powerful but the biggest limiting factor is latency. Altivec can peform 1 instruction per clock on the G5, However the pipeline is 8 levels deep thus the overhead involved in fetching data, loading registers, performing a calculation among 1-3 registers, and getting a result is prohibitively expensive. However, if you can arrange to submit 8 calculations (or more) in rapid sequence, you can keep Altivac and the CPU busy and reap great benefits.
The beauty of Cell will be in proving the ALUs with a bit more autonomy (thought not much more, they are still basically vector units), and enabling the main CPU to keep doing useful work while a number of ALUs are cranking away. Other novel design features provide for communication and synchronization with other units via remote addressing and timing (that's what those realtime clock signals are all about).
This will be very fast, and very cheap. However, all the hand waving, and theorizing this guy does about both hardware and software reads like patent bullshit.
Parent
This is what happens... (Score:2, Redundant)
As someone posted above, it seems like it would be fairly trivial to at least make a "dupe check" program that tells you whether you have linked to the same URL before...
Dataflow squared (Score:5, Interesting)
The original PS2 design was for a dataflow architecture - the Cell is a continuation (and significant evolution) of the theme. Interestingly enough, if this *does* take off it may be that the best programmers of tomorrow turn out to be the PS2 low-level guys, who've already written the algorithms that are about to be important.
In the PS2, the MIPS chip was there mainly to do the simple stuff, all the heavy lifting was done on the 2 vector processors, and they were designed to have programs uploaded into them and data streamed through them using a very flexible (chainable) DMA engine. Sounds similar (if in a limited sense) to the Cell chip itself.
Simon.
They reinvented The Amiga! (Score:5, Interesting)
A measly MIPS with hardware that is autonomous.
The only thing they need is to sync to the TV set.
Parent
Re:They reinvented The Amiga! (Score:3, Insightful)
Re:Dataflow squared (Score:3, Interesting)
The essential quote:
Yes, it's basically an improved PS2 (Score:3, Interesting)
The PS2 was revolutionary, in that it was the first successful non von Neumann machine. There have been many exotic architec
Transmeta (Score:4, Insightful)
This is a distributed-processing-capable chip. They're moving software into the chip, doing what software can do in a more compact and probably more efficient way. There's nothing revolutionary here and besides being a dupe story it's way overrated. The only attractive here is the fact PS3 will use it instead of embedding something open, like Mosix.
And no it won't "eventually take over the PC market."
Re:Transmeta (Score:3, Interesting)
There is a _lot_ of revolutionary ideas behind the Cell processor. As shown in the write-up, the Cell takes a drastic change from the conventional arithmetic-unit/cache setup. Additionally, the way the Cell can pipeline parallelizable problems amongst the 8 processing units within itself is a revolution of chip design already. Take, for example, the video encoding/decoding example shown in the write-up, whereas an an Intel chip will require processing of each procedure
Re:Transmeta (Score:3, Insightful)
Re:Transmeta (Score:3, Interesting)
Pentium-4 was an architectural mistake conceived with the goal of pushing the MHz numbers up (since the mass market appeared to trust MHz over "MHz-equivalent" labels). AMD astonished them by finally making their alternate naming scheme credible and the plan behind the P4 went straight down the crapper.
New x86 development at Intel is largely derivative of the P3 core (the family that includes the P-M) and has la
There are always critical sections (Score:5, Interesting)
There will always be "critical sections", data which can only be used by 1 thread at a time, which limits how much it can be split up.. Then you have programs which cant be.. I mean, you can split up a game for instance into a sound, video, and keyboard threads easily. To really utilise parallel processing takes a massive amount of code, which with current languages, seems to make it a bit implausible to get a massive increase.
It should also be remembered that the G5's and G4's already have altivec, and even though this is on a much grander scale, there will always be bottlenecks that slow it down preventing 99% of commonly used apps from getting a significantly large increase..
Consider a different approach (Score:5, Informative)
All the programs that run on PC architectures expect certain things to be in place - they expect a single fast central CPU. They expect that good cache usage is important for performance. They expect to have access to gobs of RAM. Etc. Etc. The PS2 (and by extension the cell) is completely different.
Consider a different architecture. You have a job that consists of multiple things to do. Some of these can be easily parallelised, others are mainly sequential. Divide it up so the parallel ones are coded separately, maybe with some IPC to synchronise to some clock.
For a sequential part (say rendering the object list of a scene back to front to gain occlusion) the approach that worked for me on the PS2 (which is logically similar, if significantly less powerful) was to divide the job into tasks. Each task (say, one per object in the above) gets its own bit of code and knows about the data that it needs to perform its task.
The key thing is that the Harvard separation of code and data just isn't, on a PS2. You set up a DMA chain that loads the program into the processor, then streams the data through the program on the processor, lather, rinse, repeat. Make the chain self-submitting and you can effectively forget about that chunk of code now, it'll just happen.
This is still doing things sequentially (but we've agreed that this is a sequential task, right?) - the point is that it's being done highly efficiently within the architectural constraints. You have a dataflow architecture and even sequential code can hit the performance limits if you code to the architecture.
The Cell looks even more powerful, in that you can chain execution modules together, so you can load code into APU's 1,2,3,4 and stream the data through 1,2,3,4 automatically before it's considered 'done'. This was possible on the PS2, but
Simon
Parent
Re:Consider a different approach (Score:3, Interesting)
I *think* the programming model will be sort-of-like CORBA, with 'messages' being sent from a central despatcher (the G5 probably, though it could be another APU). I think the messages will be self-contained program+data though - they've even called them APUlet's. The OS then schedules them to be executed on the first available APU.
The message is the data, but the code will be bundled along with it, and when it's finished, it'll send another message back to the despatcher
Re:Consider a different approach (Score:3, Interesting)
Secondly, Darwin will not need porting to the Cell. It will almost certainly run with no modification on the PU. Things like QuickTime, Quartz and CoreVideo/Audio are likely to benefit by having components run on an APU, as might things like the network stack, bu
Timothy, Saturday night (Score:5, Funny)
Some Thoughts (Score:5, Insightful)
First of all I want to say I think it is completly possible to make a processor with 8APUs and so forth. For starters PowerPC chips already have several seperate execution units on them, and I think they use fewer transitors than intel chips. Moreover, a huge chunk of the transitor budget goes to doing things like cache consistancy or complicated instruction prediction which is probably not used on the much simpler APUs.
Of course it seems like this is primarily of interest to game systems or signal processing applications (note that a 4 threaded 32 stream processors is just another way of saying 4 cell procesors, each has a PPC core with 8 APUs). However, I would not be so quick to dismiss this for the PC market. While it may be true that many individual applications may not easily multi-thread it seems we are approaching a point where the biggest complaint is not the maximum processing rate in one application but the ability to run multiple applications at once. On my computers I'm rarely if ever frustrated at the rate some program is running at, but slowdown in other programs when I run a processor intensive job or turn on a video. So while drawing a webpage may not be speed up by this processor drawing several webpages at the same time will be and that is the sort of thing which makes a big difference for the end user.
Also, a processor like this offers great possibilities for JIT and VM code. The main thread can dispatch instructions and threads to the APUs dynamically based on what is happening in the system. Also I find it interesting that IBM is going the same way as intel in pushing all the complexity on the compiler. It makes one wonder if itanium is really as dead as everyone thinks. Perhaps in 4 years when AMD can't squeeze anything more out of x86 intel will be ready to jump in having worked out all the bugs to their new chip.
Merrimack streaming processor is like CELL (Score:3, Informative)
It's so similar that you wonder if they lifted it from him. The only difference is that Prof. Dally's chip has a big cache.
What I can't help but think (Score:5, Interesting)
This is, of course, all just conjecture.
But when I begin to see people seriously talking about the chip from the Playstation 3 eventually potentially being used in PC hardware, I begin to wonder if it's maybe reasonable conjecture...
3 architectures (Score:5, Interesting)
It's been said before, but mature industries tend towards three of something, such as GM-Ford-Chrysler. For CPUs, it has to be AMD64/ia32e, PowerPC, and SPARC. They're the only ones with any high-volume prospects. SPARC will certainly be in third place, with AMD64/ia32e and PowerPC duking it out for one and two. The fact of the matter is that Itanium won't be a mainstream processor, and PA-RISC, Alpha, and MIPS are all more-or-less EOL.
For operating systems it will still be Windows, Linux, and UNIX (predominately Mac OS and Solaris). Okay, that's four, but the other historical major players are all becoming niche legacy platforms.
For office suites, it'll be MS Office, StarOffice/OpenOffice.org, and iWork. The others are all niche players.
For browsers it'll be IE, Firefox, and Safari.
At least this will tend to simplify some things, because the non-Microsoft platforms will be fewer making supporting them easier. This is a good thing, IMO.
Re:3 architectures (Score:5, Funny)
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Re:3 architectures (Score:4, Interesting)
I don't think it does. Microsoft will be around for a while, unfortunately. In my sig, I expect Solaris, Mac OS, and Linux to be the top three of the UNIX side (not necessarily in that order). The BSDs are there for completeness, as they are good systems but are niche players. The main point behind my sig is that all the options listed are either cheaper/freer than Microsoft's options or just flat out better than Microsoft's options (or both). Microsoft really is in a precarious situation, where they have only inertia carrying them at the moment (granted, it's a lot of inertia but it's definitely finite).
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Talk is cheap, and hollow hype is worthless. (Score:3, Insightful)
And if I had 4 legs, I could outrun a dog.
But I don't, so I can't. And this chip won't be as good as the (overenthusiastic) article claims. It won't take over the PC market.
This chip will take over the PC market the same way that BitBoys took over the graphics card market; the same way that Transmeta took over the mobile CPU market; the same way that the Elbrus 2k took over the desktop CPU market. That way is: deliver endless hype that you can't possibly back up. By the time it hits the market, the hype will be so built up that people won't be able to help but to feel let down by the chip. Then they'll lose interest in the product.
This chip might be fast for the money, and enable them to put 4 cores in a consumer device like the Playstation, but it's not going to outperform (or even match) a CPU like the P4 or Athlon 64.
When will people learn to stop falling for the same tricks?
No one has mentioned the Transputer (Score:3, Interesting)
Semiconductor Reporter article... (Score:4, Interesting)
Looks like pilot production should begin soon on a 90 nm. process similar to that used for current Athlon 64s and Opterons. No word in this article on initial clock speeds and power dissipation.
Anyone have additional info?
BTW, another article I hadn't seen linked [com.com] claims that Cell will be relatively easy to program...seems that Sony learned from some of its PS2 mistakes. That contradicts a lot of the threads responding to the original article and this dupe.
Re:Thats bull (Score:2)
No, it's not bull. (Score:2)
Simon.
Re:Well, this could use some more reiteration... (Score:5, Informative)
Paper Details:
Parent
Re:Steve Jobs, Vectors and OS X (Score:3, Informative)
Wrong. Jobs hired the guy who produced the Mach operating system at Carnegie Mellon, Avie Tevanian [apple.com].