A History of PowerPC

A reader writes: "There's a article about chipmaking at IBM up at DeveloperWorks. While IBM-centric, it talks a lot about the PowerPC, but really dwells on the common ancestory of IBM 801" Interesting article, especially for people interested in chips and chip design.

IBM also says Screw you to intel

IBM Also announced [tmcnet.com] a ton of new PPC information and tech today at an event in new york. Opening up the ISA to third parties including Sony.

Re:IBM also says Screw you to intel

If it's what I think it is, then Intel has been doing this since the 80386 (try VMWare, which uses your box's CPU in this way, then Bochs, which emulates an x86 CPU), Motorola (and therefore IBM, because of the AIM alliance) has been doing this since the PPC 601 (Mac-on-Linux only runs on PPCs, pretty damn obvious here, isn't it?), and it just goes on and on.

Well sort of

It's actually closer to Intel's Vanderpool [xbitlabs.com] technology that allows you to partition the cpu through firmware.

Example: Windows is running on slice 1, BSD on slice 2, and Linux on slice 3.

BSD gets a kernel panic and crashes, the slice is restarted without affecting the remaining running OS's. It's, for the lack of a better term, Hyperthreading for the whole computer.

Big Endian

I'm not a fan of big endian... or is it little endian... I dont remember, but I do know, if it's backwards, it's backwards because it's reverse of what I'm used to.

Re:Big Endian

PPC is big endian, which is normal.

X86 is little endian, which is chunked-up and backwards.

Example:
View the stored number 0x12345678.

Big endian: 12 34 56 78
Little endian: 78 56 34 12

Clear as mud?

Re:Big Endian

Motorolas PPC implementation is only partly dual-endian. The G3s are byte-sexual, most G4s are, but some G4 chipsets are not.

Re:Big Endian

Big-endian appeals to people because they learned to do their base-10 arithmetic in big-endian fashion. The most significant digit is the first one encountered. It's habit.

Little-endian has some nice hardware properties, because it isn't necessary to change the address due to the size of the operand.

Big Endian:
uint32 src = 0x00001234; // at address 1000, say
uint32 dst1 = src; // fetch from 1000 to get 00001234
uint16 dst2 = src; // fetch from 1000 + 2 to get 1234

Little Endian:
uint32 src = 0x00001234; // at address 1000, say
uint32 dst1 = src; // fetch from 1000
uint16 dst2 = src; // fetch from 1000

The processor doesn't have to modify register values and funk around with shifting the data bus to perform different read and write sizes with a little-endian design. Expanding the data to 64 bits has no effect on existing code, whereas the big-endian case will have to change all the pointer values.

To me, this seems less "chunked up" than big endian storage, where you have to jump back and forth to pick out pieces.

In any event, it seems unnecessary to use prejudicial language like "normal" and "chunked up". It's just another way of writing digits in an integer. Any competent programmer should be able to deal with both representations with equal facility.

Being unable to deal with little-endian representation is like being unable to read hexadecimal and insisting all numbers be in base-10 only. (Dotted-decimal IP numbers, anyone?)

Big-endian has one big practical advantage other than casual programmer convenience. Many major network protocols (TCP/IP, Ethernet) define the network byte order as big-endian.

Don't ignore integer sizes!

Expanding the data to 64 bits has no effect on existing code, whereas the big-endian case will have to change all the pointer values

So, you're reading in an array of integers, which are now 64 bit vs 32 bit and no code change is needed?

Programs NEED to know the size of the data they're working with. Simply pulling data from an address without caring for it's size is a recipee for disaster!

Re:Big Endian

What kind of strange CPU implementation modifies register values when addressing sub-word vlaues? This is done most commonly by the programmer at write-time, (or maybe by some strange compiler or assembler at compile-time). This is not a hardware advantage in any architecture I'm aware of. Are you perhaps talking about extra hardware burden associated with unaligned memory access? Unaligned memory access is not a consequence of byte ordering.

One more big advantage of the big-endian byte order is that 64-bit big-endian CPUs can do string comparisons 8 bytes at a time. This is a big advantage where the length of the strings is known (Java strings, Pascal strings, burrows-wheeler transform for data compression) and still an advantage for null-terminated strings.

I'm not aware of any such performance advantages for the little-endian byte order.

The main advantage of little-endian byte order is ease of modifying code written in assembly or raw opcodes if you later decide to change your design and go with larger or smaller data fields. The main uses for assembly programming are very low-level kernel programming (generally the most stable part of the kernel code base) and performace enhancement of small snippets of code that have been well tested and profiled and are unlikely to change a lot.

I agree that an decent programmer should be able to deal with either endianess, but the advantages of the little-endian byte order seem to be becoming less and less relevant.

Re:IBM also says Screw you to intel

Sony?

Does this mean that ALL next-generation consoles (next Gamebuce, PS3 and Xbox2) will use a IBM chip?

Re:IBM also says Screw you to intel

yes they are all PPC "based" now. The PS3 will be using what is called the Cell cpu which is derived from the Power ISA.

Theres a pantload of info here [ibm.com].

Re:"Chips May Physically Reconfigure Themselves"

P.S. Does anyone know why Windows has never been adapted to run under PPC?

Errm, actually, it WAS. See for instance

http://home1.gte.net/res008nh/nt/ppc/default.htm [gte.net]

Chip design in a nutshell for the lazy:

Cut up a russet potato into thin strips or wedges.

Fry in oil or bake in oven.

Salt.

Enjoy!

*sigh*

I still want a PPC ATX board. Pegasos was supposed to deliver, but their boards are still so expensive. :-(

Re:*sigh*

I still want a PPC ATX board. Pegasos was supposed to deliver, but their boards are still so expensive. :-(

Supposed to deliver? OpenBSD people thought that as well, and got the OS running on it. Now OpenBSD consider Pegasos a scam operation and has pulled the support for Pegasos from CVS :

R.I.P. OpenBSD/Pegasos - All the story [deadly.org]

Guide to the PowerPC architecture

They also have a very good article about the PowerPC's three instruction levels and how to use implementation-specific deviations, while code stays compatible. This introduction to the PowerPC application-level programming [ibm.com] model will give you an overview of the instruction set, important registers, and other details necessary for developing reliable, high performing PowerPC applications and maintaining code compatibility among processors.

Nice 42 year backward compatibility

From TFA:

"Today's IBM mainframes still maintain backwards-compatibility with that revolutionary 1962 instruction set."

Good plan then, Intel, on that whole Itanium mess.

John.

Interesting quote from the article

Buried in the middle of a section talking about CMOS, we find this:

Thus, in the days when computing was still so primitive that people thought that digital watches were a neat idea, it was CMOS chips that powered them.

You find Douglas Adams fans all over, don't you?

Obligatory Quote of the Day

"Finally, the Fishkill operation is so hip that the server room runs exclusively on Linux."

I didn't think it was possible to use the words "Fishkill" and "hip" in the same sentence with a straight face.

Power PC was the death of the MIPS processor

Not that it was necessarily a bad think, but with the PowerPC came a whole new generation of workstation.

Gone where the intelligent disk and network subsystems. No more die cast aluminimum chassis.

Whilst I can understand in some sectors the incessant drive for highest MIPS per $, is there not also a place for bullet proof proven technology?

Yeah, I remember

back in 94 or so, when the AIM were predicting that they were going to completely obliterate the x86 in a few years. Anyone still have those neat graphs that showed exactly where Intel would hopelessly fall behind while PPC would accellerate exponentially into the atmosphere?

Re:Yeah, I remember

Yes

What Intel did was include RISC architecture in around the x86 instruction set to create the pentium pro, pentium II, III, etc. Otherwise they would have been killed.

Infact IBM was correct. Cisc was dying. THe pentium1 could not compete agaisnt the powerpc unless it had a very high clock speed. All chips today are either pure risc or a hybrid cisc/risc like todays Althons/Pentium's. The exception is the nasty Itanium which is not doing too well

Nice PowerPC Roadmap

Motorola has a nice overview graphic [motorola.com] - you can also checkout a more generalized article at The Star Online [star-techcentral.com].

PowerPC in PlayStation 2? Huh?

...the PowerPC core is really fast and really tiny (leaving lots of room on the chip for customization), and also because the PowerPC architecture is amenable to being coupled with more than one additional coprocessor. This explains its success in highly specialized environments like set-top boxes or the GameCube and Playstation2 video game consoles.

Correct me if I'm wrong, but isn't the PlayStation 2's EmotionEngine processor a proprietary MIPS-derived ISA?

Re:PowerPC in PlayStation 2? Huh?

The core has a full mips-3 instruction set, with extensions from mips-4 and mips-5
link [uiuc.edu]

So yes, it is in a way MIPS derived, but the MIPS core does very little of the actual processing, it's more of a bootloader and I/O coprocessor.

So what HDL do they use?

VHDL, Verilog, something else entirely?

Re:So what HDL do they use?

When I was working on the embedded IBM PowerPCs (400 series), we used Verilog primarily...though there were a few VHDL hold-outs.

One of the coolest things about PowerPC chips

Is its revolutionary three level cache architecture, utilising a 3-way 7 set-transitive cache structure, which gives performance equivalent to a 2-level traditional x86 style cache for more content addressable memory. Each processor has a direct triple-beat burstless fly-by cache gate interface capable of fourteen sequential memory write cycles, including read/write-back and speculative write-thru on both the instruction and data caches. Instruction post-fetch, get-post, roll-forward and cipher3 registers further enhance instruction cache design, and integrated bus snooping guarantees cache coherency on all power PC devices with software intervention. Special cache control and instructions were necessary to control this revolutionary design, such as 'sync', which flushes the cache, and the ever-popular 'exeio' memory fence-case instruction, named after the line in the popular nursery rhyme.

Computer history IS IBM-centric

I don't see how computer history that goes back to the 1960s can fail to be "IBM-centric." Remember, these were the big guys Microsoft was afraid of pissing off in the 1970s and 1980s. No one ever got fired for buying IBM, because they pretty much wrote the book on chip design before Intel hit it big.

For those who want PPC970 without getting a Mac...

You should check out: Momentum Computer [970eval.com]

Sure its pricey, but I suppose if your interested in such price isn't the key issue.

Sunny Dubey

Re:For those who want PPC970 without getting a Mac

Geez, I can't believe I'm saying this, but it would be cheaper to just buy a Mac.

LK

Re:For those who want PPC970 without getting a Mac

Or, you could always settle for an RS/6000.

RS/6000 [ibm.com]

Or, a Power-based IBM workstation,

Workstation [ibm.com]

About My Resume...

IBM's John Cocke was no stranger to the battle against complexity. He had already worked on the IBM Stretch computer

Not sure I'd want that on my resume. Wasn't IBM's greatest success -- even given their unmatched maketing department.

200 instructions at once?

I think it's quite imprecise writing for the article to state (several times, for POWER4 and the PowerPC 970) that they "can process 200 instructions at once at speeds of up to 2 GHz." That makes it sound like they can finish 200 instructions at once, which is silly. I imagine what they really mean is that there can be up to 200 instructions in flight in the pipeline at a time.

(Which is great until you mispredict a branch, of course. :-)

Re:200 instructions at once?

Yeah. It's a good thing that the processors in the POWER line has unbelievable branch prediction logic. So, for example, the branch prediction rate for the POWER 4 is in the mid to high 90 percentile for most workloads (as high as 98%, IIRC) In fact, quite a large number of transitors are dedicated to this very topic, which allows the processor to do a pretty good job of achieving something close to it's theoretical IPC.

Although, it should be noted that the pipeline depth for the POWER4 is just 15 stages (as opposed to the P4 which has, IIRC, 28 stages), so while a branch misprediction is quite bad, it's not as bad as some architectures. My understanding is that, in order to achieve that 200 IPC number, the POWER4 is just a very wide superscalar architecture, so it simply reorders and executes a lot of instructions at once. Plus, that number may in fact be 200 micro-ops per second, as opposed to real "instructions" (although, that's just speculation on my part... it's been quite a while since I read up on the POWER4), as the POWER4 has what they term a "cracking" stage, similar to most Intel processors, where the opcodes are broken down into smaller micro-ops for execution.

Quotable!

[The RS64's] qualities make it ideal for things like on-line transaction processing (OLTP), business intelligence, enterprise resource planning (ERP), and other large and hyphenated, function-rich, database-enabled, multi-user, multi-tasking jobs

Large and hyphenated! It's nice when technical writers get to slip a little something in on the side.

Article may need a bit of work

Are you really saying that the POWER3 was built with the same 15M transistors as the POWER2?

Also, when you say that POWER4/PPC970 can process 200 instructions at once, you need to explain a bit better what having "instructions in flight" really means. It's not that it can do 200 instructions every clock cycle.

Submitted this on the feedback form at the bottom of the article as well. The above just don't ring right as expressed.

Sounds fishy to me...

...Even x86 chip manufacturers, which continued for quite a time to produce CISC chips, have based their 5th- and 6th-generation chips on RISC architectures and translate x86 opcodes into RISC operations to make them backwards-compatible...

Maybe this is a sign that it has been too long since I learned about computer architecture, but is it really fair to call a CPU that has a deep pipeline, a crypto-RISC CPU?

When my buddy first told me about this exciting new RISC idea one of the design goals was each instruction was to take a single instruction cycle to execute. Isn't this completely contrary to a deep pipeline? The Pentium 4 has a 20-stage pipeline IIRC.

Was I wrong to laugh when I heard hardware manufacturers claim, "sure, we make a CISC, but it has RISC-like elements .

What I am reminded of is the change in how musicians are classified. When I grew up rock music was just about all that young people listened to. Rap and punk music had never been heard of. And country music was considered incredibly uncool. Now country music's coolness factor has grown considerably. And a strange thing has happened. Lots of artists who were unquestionably considered in the Rock camp back then, like Neil Young, or Credence Clearwater, are now classified as Country music, as if they had never been anything else.

It has been a long time, but I remember learning in my computer architecture course about wide microcode instruction words, and narrow microcode instruction words. Wide microcode instruction words allowed the CPU to do more operations in parallel. Ie. the opposite of a RISC. So, I ask in perfect ignorance -- how wide are the Pentium 4 and Athlon microcode?

If I am not mistaken the Transmeta was a very wide instruction word. And if I am not mistaken, doesn't that make it the opposite of a RISC?

Re:Sounds fishy to me...

When my buddy first told me about this exciting new RISC idea one of the design goals was each instruction was to take a single instruction cycle to execute. Isn't this completely contrary to a deep pipeline?

No, in fact pipelining is central to the entire concept of RISC.

In traditional CISC there was no pipelining and operations could take anywhere from 2-n cycles to complete -- at the very least you would have to fetch the instruction (1 cycle) and decode the instruction (1 cycle; no, you can't decode it at the same time you fetch it -- you must wait 1 cycle for the address lines to settle, otherwise you cannot be sure of what you're actually reading). If it's a NOOP, there's no operation, but otherwise it takes 1+ cycles to actually execute -- not all operators ran in the same amount of time. If it needs data then you'd need to decode the address (1 cycle) and fetch (1 cycle -- if you're lucky). Given that some operators took multiple operands you can rinse and repeat the decode/fetch several times. Oh, and don't forget about the decode/store for the result. So, add all that up and you could expect an average instruction to run in no less than 7-9 cycles (fetch, decode, fetch, decode, execute, decode, store). And that's all presuming that you have a memory architecture that can actually produce instructions or data in a single clock cycle.

In RISC you pipeline all of that stuff and reduce the complexity of the instructions so that (optimally) you are executing 1 instruction/cycle as long as the pipelines are full. You have separate modules doing the decodes, fetches, stores, etc. (and in deep-pipeline architectures, like the P4, these steps are broken up even more). This lets you pump the hell out of the clockrate since there's less for each stage of the pipeline to actually do.

Modern CPUs have multiple everything -- multiple decoders, fetchers, execution units, etc. so it's actually possible to execute >1 cycle/cycle. Of course, the danger to the pipelining is that if you branch (like when a loop runs out or an if-then-else case) then all those instructions you've been decoding go out the window and you have to start all over from wherever the program is now executing (this is called a pipeline stall and is very costly; once you consider the memory delays it can cost hundreds of cycles). Branch prediction is used to try and mitigate this risk -- generally by executing both branches at the same time and only keeping the one that turns out to be valid.

Was I wrong to laugh when I heard hardware manufacturers claim, "sure, we make a CISC, but it has RISC-like elements .

Yes, because neither one exists anymore. CISC absorbed useful bits from RISC (like cache and pipelining) and RISC realized there was more to life than ADD/MUL/SHIFT/ROTATE (oversimplification of course). The PowerPC is allegedly a RISC chip, but go check on how many operators it actually has. And note that not all of them execute in one cycle. x86 is allegedly CISC, but, well... read on.

how wide are the Pentium 4 and Athlon microcode?

The x86 ISA has varying width. It's one of the many black marks against it. Of course, in reality, the word "microcode" isn't really applicable to most CPUs nowadays -- at least not for commonly used instructions. And to further muddy the picture both AMD and Intel don't actually execute x86 ISA. Instead there's a translation layer that converts x86 into a much more RISC-y internal ISA that's conducive to running at more than a few megahertz. AFAIK, the internal language is highly guarded by both companies.

If I am not mistaken the Transmeta was a very wide instruction word. And if I am not mistaken, doesn't that make it the opposite of a RISC?

Transmeta and Intel's Itanium use VLIW (very large instruction word) computing, which is supposed to make the hardware capable of executing multiple dependant or independant operations in one cycle. It does so by putting the onus on the compiler

I like this quote

The 64-bit PowerPC 970, a single-core version of the POWER4, can process 200 instructions at once at speeds of up to 2 GHz and beyond -- all while consuming just tens of watts of power. Its low power consumption makes it a favorite with notebooks and other portable applications on the one hand, and with large server and storage farms on the other.

Can anyone tell me where I can buy a G5 laptop?

Next Apple Mac?

Macosrumors.com has an article suggesting an IBM chip known as the PPC975 may be used for future Apple Macintosh computers at speeds of up to 3Ghz.

http://www.macosrumors.com/33004M.html

Please note that MOSR has a long history of being completely and utterly wrong in their predictions, so don't get your hopes too high...

On a similar note...

IBM announced today that they will be offering more information on the architecture of its PowerPC and Power server chips to device makers and software developers. [com.com] First software with Linux, and now hardward with their own Power Line. If intel can only do this for the Centrino line. :-/

Did anybody catch the Mars Pathfinder reference?

"The RSC implementation of the POWER1 microprocessor was used as the central processor for the Mars Pathfinder mission and is the chip from which the PowerPC line is descended"

I guess that's why it's still up there, not bluescreened...

This is revolutionary: Self-evolving machines.

I figured /. would have a lot more discussion of the Terminator-like aspects of today's announcement.

Did you read this? [businesswire.com] Look at the second-to-last paragraph:

"...IBM is working on future Power chips that can physically reconfigure themselves -- adding memory or accelerators, for example -- to optimize performance or power utilization for a specific application."

That is the first step in self-evolving machines.

Yes, it is a minor step, but it is a friggin first step, OK? If they can pull this off, they are creating machines with the ability to adapt and evolve.

This is what I would call artificial life. Once that step is taken, it's only a matter of time before the machines start evolving themselves.

P.S. Now think about the kinds of viruses that could happen in that environment.

The complete history

I found this site a couple years ago, and i'm sure everyone has heard of it, but just in case: apple-history.com [apple-history.com]

Best article ever!

Seriously, check these quotes from the IBM site: [blockquote] Thus, in the days when computing was still so primitive that people thought that digital watches were a neat idea, it was CMOS chips that powered them. [/blockquote] [blockquote]Figure 1. It's wafer-thin[/blockquote] [blockquote]One of the reasons for that is IBM's new top-of-the-line fab in Fishkill, New York. The Fishkill fab is so up-to-date that it is capable of producing chips with all of the latest acronyms, from copper CMOS XS to Silicon-on-Insulator (SoI), Silicon Germanium (SiGe), and low-k dielectrics -- all on 300mm wafers. And the Fishkill facility is so advanced that the workers don't even have to wear "bunny suits," because the wafers spend all of their time in hermetically sealed FOUPs (front opening unified pods). Finally, the Fishkill operation is so hip that the server room runs exclusively on Linux.[/blockquote]

Something wrong?

Help me out here. A quote from the article is:

POWER3
Released in 1998: 15 million transistors per chip
The first 64-bit symmetric multiprocessor (SMP)

Didn't several companies have 64-bit multiprocessor machines out back then? Unless I'm mistaken, Sun's Starfire was before then, having up to 64 UltraSparc II's - which, as I recall, were 64-bit chips. And that's just Sun, ignoring the other players.

So, it is just that they used "SMP", as opposed to other forms of multiprocessing, or is my memory completely skewed?

steve

Impressive

"What do the Nintendo GameCube's Gekko, Transmeta's first Crusoe chips, Cray's X1 supercomputer chips, Xilinx Virtex-II Pro processors, Agilent Tachyon chips, and the next-generation Microsoft XBox processors-which-have-yet-to-be-named all have in common? All of them were or will be manufactured by IBM."

That's quite impressive. Throw the 970 in that mix and it's even more impressive. The bottom line is that Intel isn't alone at the top of the mountain when it comes to producing high quality, fast, and reliable chips. On a side note, as a soon-to-be-graduating CS major, I dream about working at a place like IBM.

Orthogonal?

Most of the computers of the day, such as the IBM S/360 mainframe, had complex and redundant (or "orthogonal") instruction sets

Surely they mean NON-orthogonal?

Redundant (i.e. "Orthogonal") WTF???

to quote the Jargon file:

Orthogonal: Mutually independent; well separated; sometimes, irrelevant to. Used in a generalization of its mathematical meaning to describe sets of primitives or capabilities that, like a vector basis in geometry, span the entire 'capability space' of the system and are in some sense non-overlapping or mutually independent.

to quote the article: ...such as the IBM S/360 mainframe, had complex and redundant (or "orthogonal") instruction sets...

Othogonal is pretty damn close to an antonym of "complex and redundant". In fact, a RISC ISA should be as orthogonal as practical (under the other constraints of constant word size etc.)

While we are at it, the article notes:
"All of that changed back in the thermionic valve (or "vacuum tube") days with the introduction of the IBM S/360(TM) line of computers, in 1964."

Huh? IBM was producing "transfer resistor" ("transistor") computers by the 1960's and the 360 was based on those newfangled "integrated circuits" (or "chips"). At that point tubes were as anachronistic as they are now!

One last howler: the sidebar title "Breaking the speed limits of Moore's Law" I always thought gemometric rates of increase didn't class as a speed limit as much as a brutal taskmaster, if the Transportation Department legislated a doubling of speed every 16 months beginning in 1960, transwarp drives would be required equipment on cars since we would have a minimum speed limit of warp 44!

What Pisses Me off

I bought IBM stock at 99 per share than again at 92 a share, i was sure it was going to split but all its been doing is falling. i was hoping that all of the new things theyve been doing would drive their stock though the roof bu nothings happening. im starting to think that all stock traders need an IT lesson.
But seriosly, i wounder if sun will end up standardising on the PPC or the AMD 64 chips. their own proccesors are a little long on the tooth.

XBox Next CPU?

From the article:

"What do the Nintendo GameCube's Gekko, Transmeta's first Crusoe chips, Cray's X1 supercomputer chips, Xilinx Virtex-II Pro processors, Agilent Tachyon chips, and the next-generation Microsoft XBox processors-which-have-yet-to-be-named all have in common? All of them were or will be manufactured by IBM."

What the hell? I thought the XBox Next CPU being a PowerPC was still an unconfirmed rumor?

Re:Motorola

Motorola didn't give up on PPC.

They gave up on desktop PPC. They still do a lot of new PPCs, just working on improving MIPS/watt instead of pure MIPS. Embedded space is a lot higher volume and bigger profit than Apple.

Re:Motorola

I've seen this myth repeated again and again, usually in conjunction with conspiracy theories like "Motorola quit developing the G4 to hurt Apple".

1) 80% of all G4s sold have gone to Apple. So targetting the larger embedded market is a marketing excuse, a failure, or both.

2)Motorola's fabrication facilities have been in horrendous shape for at least 4 years. High failure rates, In one location, they even quit running the fans to "save energy."

3)Motorola has failed to advance in the embedded world as well. TiVO and many others are switching from PPC to MIPS because Motorola's stuff is not moving forward.

4)Brain-drain and 'Dilbert syndrome' have plagued Motorola's CPU division since Apple killed the clones in 1997. They are spinning off that part of their business, but there's no indication that the situation has improved.

Re:Motorola

Motorola did make a decent range of PPC based boxes. They could run NT (but the PPC version of NT never worked very well), they could run Unix (but legacy app varieties, and thiers was an incongruous multimedia box in that environment). It was supposed to run Apple, but I never saw that.

Yes, Motorola did build and promote thier hardware, but OS manufacturers did not even seem to be able to get decent device drivers working for it, let alon do an efficient port. In the end it was a box that could (almost) do many things, but at a higher price for less performance. They threw in the towel.

BTW, I did build a server using a Motorola motherboard and standard PC parts. It ran Aix 4 fine, but forget decent video drivers let alone sound. I did try getting the PPC port of Linux up on it, but never succeeded. It did run very stably as a server. It wasn't lightning fast but seemed to scale perfectly, it just kept chugging alone regardless of the workload you threw at it.

I say blame the OS manufacturers for Motorolas lack of success with the PPC.